专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4516218A Memory system with single command selective sequential accessing of predetermined pluralities of data locations 失效
标题翻译：具有单个命令的存储系统选择性地顺序访问预定的多个数据位置
公开(公告)号：US4516218A
公开(公告)日：1985-05-07
申请号：US163025
申请日：1980-06-26
申请人： Stephen P. Hamilton
发明人： Stephen P. Hamilton
IPC分类号： G06F1/00 , G06F9/312 , G11C5/14 , G06F9/32 , G06F13/06 , G06F15/02
CPC分类号： G06F9/30043 , G06F1/00 , G11C5/141
摘要： This addressing system, advantageously for smaller scale data processors with relatively narrow data paths, facilitates transferring pluralities of multibit data words, e.g., storing or fetching the contents of a multidigit register in a calculator. A bidirectional bus couples a controller and a plug-in memory. The controller generates address, data, and command signals. A decoder receives command signals and outputs signals to a program counter (PC) alternatively indicating a normal mode, in which the controller accesses a single specified memory address, or a multiple access mode, in which a predetermined number of sequential addresses are accessed starting at a specified address. In response to selective command decoder output, the PC alternatively may store received addresses, output stored count values to the controller or to a memory array, or increment the count value in synchronism with data transfers to/from multiple memory locations. The decoder, PC, and memory array are contained within the portable memory module's housing, which may be mounted in another housing containing the controller.In a ROM embodiment, the mounted memory is powered directly from a source in the controller housing. In a RAM embodiment, the module's housing includes a power switching circuit and an internal battery to provide uninterrupted power to the read/write memory cells irrespective of whether the module is mounted or detached.
摘要翻译：该寻址系统有利地用于具有相对窄的数据路径的较小规模的数据处理器，有利于传送多个数据字数据，例如在计算器中存储或取出多位寄存器的内容。双向总线耦合控制器和插件存储器。控制器产生地址，数据和命令信号。解码器接收命令信号并将信号输出到程序计数器（PC），指示正常模式，其中控制器访问单个指定的存储器地址或多址存取模式，其中从一个指定的地址。响应于选择性命令解码器输出，PC可替代地存储接收到的地址，将存储的计数值输出到控制器或存储器阵列，或者与向多个存储器位置的数据传输同步地增加计数值。解码器，PC和存储器阵列包含在便携式存储器模块的壳体内，其可以安装在包含控制器的另一壳体中。在ROM实施例中，安装的存储器直接从控制器壳体中的源供电。在RAM实施例中，模块的外壳包括电源开关电路和内部电池，以便不管模块是安装还是拆卸，都可以向读/写存储单元提供不间断电源。

2. 发明授权

US4443845A Memory system having a common interface 失效
标题翻译：存储器系统具有公共接口
公开(公告)号：US4443845A
公开(公告)日：1984-04-17
申请号：US163023
申请日：1980-06-26
申请人： Stephen P. Hamilton , Arthur C. Hunter
发明人： Stephen P. Hamilton , Arthur C. Hunter
IPC分类号： G06F9/34 , G06F1/00 , G06F9/312 , G06F13/16 , G06F15/02 , G11C5/14 , G06F13/06
CPC分类号： G06F9/30043 , G06F1/00 , G11C5/141
摘要： A data processing system having separate read-only memory and read-write memory integrated circuits coupled to a central processing unit via the same interface system. The data processing system is comprised of bus means having either command, address, or data signals present and conducted thereon. In the preferred embodiment, the bus means is comprised of a four binary digit bidirectional conductor bus coupling between the central processing circuit and the memory circuits. In the preferred embodiment, the data processing system is further comprised of processor means within said central processing unit coupled to the bus means for selectively transmitting selected ones of said command, data and address signals onto the bus means, said processor means further including means for receiving certain other ones of said data and address signals from the bus means; and memory means including, in the preferred embodiment, read-only memory circuits and read write memory circuits, coupled to the bus means (and to the processor means via the bus means), including means for selectively transferring data with the processor means in response to said received command and address signals being within a unique subset of commands and addresses. In the preferred embodiment, each separate individual circuit comprising the memory means includes the means for responding to the command signal received via the bus means and for storing or outputting address signals or data signals responsive to decoding said received command signal.
摘要翻译：具有分离的只读存储器和读写存储器集成电路的数据处理系统，其通过相同的接口系统耦合到中央处理单元。数据处理系统包括具有存在并在其上传导的命令，地址或数据信号的总线装置。在优选实施例中，总线装置由在中央处理电路和存储器电路之间的四位二进制数双向导体总线耦合组成。在优选实施例中，数据处理系统还包括与所述总线装置相连的所述中央处理单元内的处理器装置，用于选择性地将所选命令，数据和地址信号传送到总线装置上，所述处理器装置还包括：从所述总线装置接收所述数据和地址信号中的某些其他信号; 以及在优选实施例中包括耦合到总线装置（以及经由总线装置到处理器装置）的只读存储器电路和读写存储器电路的存储器装置，包括用于响应于选择性地与处理器装置传送数据的装置所述接收到的命令和地址信号在命令和地址的唯一子集内。在优选实施例中，包括存储装置的每个单独的单独电路包括用于响应经由总线装置接收到的命令信号并用于响应于解码所接收的命令信号来存储或输出地址信号或数据信号的装置。

3. 发明授权

US4430724A Memory interface system having combined command, address and data buss 失效
标题翻译：具有组合命令，地址和数据总线的存储器接口系统
公开(公告)号：US4430724A
公开(公告)日：1984-02-07
申请号：US163024
申请日：1980-06-26
申请人： Stephen P. Hamilton , Arthur C. Hunter , Kenneth A. Lies
发明人： Stephen P. Hamilton , Arthur C. Hunter , Kenneth A. Lies
IPC分类号： G06F1/00 , G06F9/30 , G11C5/14 , G06F13/06
CPC分类号： G11C5/141 , G06F1/00 , G06F9/30
摘要： A memory interface system employs a communications protocol to distinguish between command signals, address signals and data signals appearing on the same bus lines. Each memory coupled to the bus lines detects the change between a default state on the bus lines and a command signal. A detector within each memory determines from the received command signal the type of memory operation to be performed and prepares the memory for that operation. These operations may include reading or writing data within specified locations in the memory or reading or writing within the program counter associated with the memory. The detector is only responsive to received command signals when a predetermined state follows the default state.
摘要翻译：存储器接口系统采用通信协议来区分出现在相同总线上的命令信号，地址信号和数据信号。耦合到总线的每个存储器检测总线上的默认状态与命令信号之间的变化。每个存储器内的检测器根据接收到的命令信号确定要执行的存储器操作的类型，并为该操作准备存储器。这些操作可以包括在存储器中的指定位置内读取或写入数据，或者在与存储器相关联的程序计数器内读取或写入数据。当预定状态遵循默认状态时，检测器仅响应于接收到的命令信号。

4. 发明授权

US4078251A Electronic calculator or microprocessor with mask logic effective during data exchange operation 失效
标题翻译：具有掩模逻辑的电子计算器或微处理器在数据交换操作期间有效
公开(公告)号：US4078251A
公开(公告)日：1978-03-07
申请号：US736272
申请日：1976-10-27
申请人： Stephen P. Hamilton
发明人： Stephen P. Hamilton
IPC分类号： G06F9/308 , G06F15/02 , G06F15/20
CPC分类号： G06F9/30018 , G06F15/02
摘要： An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable by the address register, and instruction word decoder logic for decoding the instruction words and for controlling the arithmetic unit in response thereto. The system further preferably includes a plurality of operational registers for storing numeric data received from the input or outputted by the arithmetic unit and a plurality of operational register selector gates coupling the operational registers with the arithmetic unit or with each other. The instruction word decoder logic includes mask logic for generating mask signals to the plurality of operational register selector gates. Thus the instruction word decoder logic decodes instructions for operating selected ones of the plurality of operational registers to effect arithmetic operations by coupling selected operational registers to the arithmetic unit or data exchange operations by coupling selected operational registers together. The mask logic also controls the selected operational registers for determining what portions of the words of numeric data stored in the operational registers are to be operated on arithmetically by the arithmetic unit or to be exchanged during data exchange operations.
摘要翻译：具有键盘输入和视觉显示的类型的电子计算器或微处理器系统通过具有运算单元的半导体芯片，响应于输入的地址寄存器来实现，指令字存储器，用于存储多个指令字，并且可由地址寄存器和指令字解码器逻辑，用于对指令字进行解码并用于响应于此控制算术单元。该系统还优选地包括多个用于存储从运算单元输入或输出接收的数值数据的操作寄存器和多个操作寄存器选择器门，其将操作寄存器与运算单元或彼此耦合。指令字解码器逻辑包括用于向多个操作寄存器选择器门产生屏蔽信号的掩码逻辑。因此，指令字解码器逻辑解码用于操作多个操作寄存器中的选定操作寄存器的指令，以通过将所选择的操作寄存器耦合在一起而将所选择的操作寄存器耦合到算术单元或数据交换操作来进行算术运算。屏蔽逻辑还控制所选择的操作寄存器，用于确定存储在操作寄存器中的数字数据的哪些字的哪些部分将由算术单元以算术运算或在数据交换操作期间进行交换。

5. 发明授权

US4020465A Thermal line printer 失效
标题翻译：热线打印机
公开(公告)号：US4020465A
公开(公告)日：1977-04-26
申请号：US428492
申请日：1973-12-26
申请人： Michael J. Cochran , Stephen P. Hamilton
发明人： Michael J. Cochran , Stephen P. Hamilton
IPC分类号： G06K15/02 , G06F3/12 , H04L15/24
CPC分类号： G06K15/028
摘要： A thermal line printer includes a semiconductor chip for control of A .times. N heaters arrayed in N groups past which thermally sensitive paper is stepped B times in printing a line of characters in an A .times. B dot matrix. A sequential access memory stores N multibit words, one word for each character to be printed on a given line with a commutator cyclically to read words from the memory A .times. B times for each line to be printed. A ROM has an A .times. B dot matrix code therein for each available character. A time sequencer and decoder connected to the ROM is synchronized with the commutator to produce a different one bit output from the ROM each time each given word is read from memory. A set of N enable circuits leads from the ROM to N groups of heaters. A set of A enable circuits leads from the sequencer to A groups of heaters where one heater in each A group is from one of the N groups. A decoder interfaces the sequencer to the A groups of heaters and to the motor sequentially to enable the heaters in one A group for each memory cycle and in order through the A columns and B rows of the matrix.
摘要翻译：热线打印机包括用于控制以N组排列的A x N加热器的半导体芯片，其中热敏纸在A×B点阵列中打印一行字符是阶梯B次。顺序访问存储器将N个多位字存储在一个给定行上的每个字符的一个字，循环地用换向器从每个行被打印的存储器读取字B×B次。对于每个可用字符，ROM中具有A×B点阵码。连接到ROM的定时器和解码器与换向器同步，每当从存储器读取每个给定字时，从ROM产生不同的一位输出。一组N个使能电路从ROM引导到N组加热器。一组A使能电路从定序器引导到一组加热器，每组A组中的一个加热器来自N组之一。解码器将定序器与A组加热器和电机顺序接口，以使每个存储器周期中的一组A组中的加热器顺序通过矩阵的A列和B行。

6. 发明授权

US4000393A Thermal printhead assembly 失效
标题翻译：热敏打印头组件
公开(公告)号：US4000393A
公开(公告)日：1976-12-28
申请号：US501919
申请日：1974-08-29
申请人： Michael J. Cochran , Larry D. Propst , Richard D. Harris , Robert E. Belland , John W. Richardson , Stephen P. Hamilton
发明人： Michael J. Cochran , Larry D. Propst , Richard D. Harris , Robert E. Belland , John W. Richardson , Stephen P. Hamilton
IPC分类号： H05B3/06 , H05B1/00
CPC分类号： H05B3/06
摘要： A method of assembling, positioning, and making connections to a thermal printhead is disclosed. A substrate is provided upon which heating elements or mesas are mounted. Leads from these heating elements are continued on the same side of the substrate as the one on which the elements are located. The leads are brought to terminal pads where connections may be made to the logic circuit which selectively energizes the heating elements to form numerals or characters on heat sensitive paper. A flat flexible cable with conductor ends exposed is held in place so that the exposed conductor ends make contact with the terminal pads of one or more of such substrates. The substrates and cable are clamped together by two metal plates. This entire assembly is mounted on a spring-loaded pivot arrangement so as to hold the heating elements against the heat sensitive paper on an advancing platen. Connections may be made between the cable conductors and the printing logic to allow the heating elements to be energized.
摘要翻译：公开了一种组合，定位和连接热敏打印头的方法。设置有加热元件或台面安装的基板。来自这些加热元件的引线在与元件所在的基板相同的一侧上继续。引线被带到端子焊盘，其中可以对逻辑电路进行连接，逻辑电路选择性地激励加热元件以在热敏纸上形成数字或字符。导体端部露出的扁平柔性电缆被固定到位，使得暴露的导体端部与一个或多个这样的基板的端子焊盘接触。基板和电缆通过两个金属板夹在一起。该整个组件安装在弹簧加载的枢转装置上，以将加热元件保持在前进压板上的热敏纸上。可以在电缆导体和打印逻辑之间进行连接，以允许加热元件被通电。

7. 发明授权

US4419746A Multiple pointer memory system 失效
标题翻译：多指针存储系统
公开(公告)号：US4419746A
公开(公告)日：1983-12-06
申请号：US196808
申请日：1980-10-14
申请人： Arthur C. Hunter , Stephen P. Hamilton
发明人： Arthur C. Hunter , Stephen P. Hamilton
IPC分类号： G06F12/02 , G11C8/00 , G11C13/00
CPC分类号： G11C8/00 , G06F12/0207
摘要： A memory system includes a multiple memory pointer in which a pointer selection signal selects one of a plurality of memory pointers to generate an address signal for application to the memory for controlling the location of memory operations. In the preferred embodiment the memory is arranged in an X by Y matrix having X times Y individually addressable memory locations. A first pointer circuit has a plurality of address pointers, one of which is selected for generation of an X coordinate address. A second pointer circuit includes a single address pointer for generation of the Y coordinate address. The second pointer circuit may be a multiple pointer in an alternative embodiment. By provision of a number of individually addressable memories responsive to the same memory pointer system, separate application of address signals from differing address pointers to differing memories permits multiple memory operations in a single instruction cycle.
摘要翻译：存储器系统包括多存储器指针，其中指针选择信号选择多个存储器指针之一以产生用于应用于存储器的地址信号，用于控制存储器操作的位置。在优选实施例中，存储器被布置在具有X次Y个别可寻址存储器位置的X乘Y矩阵中。第一指针电路具有多个地址指针，其中之一被选择用于生成X坐标地址。第二指针电路包括用于生成Y坐标地址的单个地址指针。第二指针电路可以是替代实施例中的多指针。通过提供响应于相同的存储器指针系统的多个可单独寻址的存储器，将地址信号从不同的地址指针分离到不同的存储器，允许在单个指令周期内的多个存储器操作。

8. 发明授权

US4145756A Thermal line printer 失效
标题翻译：热线打印机
公开(公告)号：US4145756A
公开(公告)日：1979-03-20
申请号：US748076
申请日：1976-12-06
申请人： Michael J. Cochran , Stephen P. Hamilton
发明人： Michael J. Cochran , Stephen P. Hamilton
IPC分类号： G06K15/02 , G08B5/36
CPC分类号： G06K15/028
摘要： A thermal printer system for actuating a plurality of groups of thermal printing elements. The system includes a first circuit in which a plurality of data words are stored, the words representing the characters to be printed. A second circuit converts the data words into printing character codes. A selected bit from each code, which bit is sequentially altered, is supplied to a third circuit for actuating the printing elements.
摘要翻译：一种用于致动多组热敏打印元件的热敏打印机系统。该系统包括其中存储多个数据字的第一电路，表示要打印的字符的字。第二个电路将数据字转换成打印字符代码。来自每个代码的选择的位被顺序地改变，被提供给用于致动打印元件的第三电路。

9. 发明授权

US4125830A Alphanumeric display system 失效
标题翻译：字母数字显示系统
公开(公告)号：US4125830A
公开(公告)日：1978-11-14
申请号：US658793
申请日：1976-02-17
申请人： Michael J. Cochran , Stephen P. Hamilton
发明人： Michael J. Cochran , Stephen P. Hamilton
IPC分类号： G09G3/14 , G06K15/18
CPC分类号： G09G3/14
摘要： An alphanumeric display system which may be implemented on one or more semiconductor chips for controlling display devices arrayed in N groups, each group of which comprises an A by B matrix of devices and which is capable of displaying a single alphanumeric character. The display devices in each group are sequentially addressed with display commands being communicated therewith in a predetermined manner to cause the display devices to visually display a predetermined alphanumeric character. Use of the alphanumeric display system herein disclosed, permits a total of A by B by N display devices to be controlled by the display system using as few as A + B + N connecting conductors to control the display devices and associated display driver devices.
摘要翻译：可以在一个或多个半导体芯片上实现的用于控制以N组排列的显示设备的字母数字显示系统，每个组包括设备的A乘B矩阵，并且能够显示单个字母数字字符。每组中的显示装置按照预定方式与显示命令进行顺序寻址，以使显示装置可视地显示预定的字母数字字符。使用本文公开的字母数字显示系统，允许N显示设备的总共A乘B由显示系统使用少至A + B + N连接导体来控制显示设备和相关显示驱动器设备。

10. 发明授权

US4503494A Non-volatile memory system 失效
标题翻译：非易失性存储器系统
公开(公告)号：US4503494A
公开(公告)日：1985-03-05
申请号：US163237
申请日：1980-06-26
申请人： Stephen P. Hamilton , Harry G. McFarland
发明人： Stephen P. Hamilton , Harry G. McFarland
IPC分类号： G06F1/00 , G06F9/312 , G11C5/14 , G06F7/38 , G06F1/04 , H02J9/04
CPC分类号： G06F9/30043 , G06F1/00 , G11C5/141
摘要： Disclosed is a non-volatile memory system which includes a first power means for providing a main power source; a read/write memory means for storing and retrieving data signals so long as power is provided; and second power means for coupling to the first power means and to the read/write memory means, the second power means including auxiliary power means for providing a second power source; the second power means further including controller means for continuously providing power to the read/write memory means from either the first power means or the auxiliary power means. In the preferred embodiment, the first power means is within a housing, said housing having a compartment for the receipt of a plug-in module, and the second power means and read/write memory means are contained within the plug-in module. Additionally, in the preferred embodiment, the memory means and the second power means exclusive of the second power source are comprised of a single integrated circuit. Furthermore, in the preferred embodiment, the power controller and memory system are coupled to a data processing system such as an electronic calculator.
摘要翻译：公开了一种非易失性存储器系统，其包括用于提供主电源的第一电源装置; 读/写存储装置，用于在提供电力的情况下存储和检索数据信号; 以及用于耦合到第一功率装置和读/写存储装置的第二功率装置，第二功率装置包括用于提供第二电源的辅助功率装置; 第二电源装置还包括用于从第一电源装置或辅助电源装置连续向读/写存储装置供电的控制装置。在优选实施例中，第一动力装置在壳体内，所述壳体具有用于接收插件模块的隔室，并且第二动力装置和读/写存储装置被包含在插入式模块内。此外，在优选实施例中，除了第二电源之外的存储装置和第二功率装置由单个集成电路组成。此外，在优选实施例中，功率控制器和存储器系统耦合到诸如电子计算器的数据处理系统。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式