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1. 发明申请

US20110196950A1 NETWORK CONTROLLER CIRCUITRY TO INITIATE, AT LEAST IN PART, ONE OR MORE CHECKPOINTS 有权
标题翻译：网络控制器电路至少部分启动，一个或多个检查点
公开(公告)号：US20110196950A1
公开(公告)日：2011-08-11
申请号：US12704240
申请日：2010-02-11
申请人： Keith D. Underwood , David N. Lombard , Jan Uerpmann , Steffen Kosinski
发明人： Keith D. Underwood , David N. Lombard , Jan Uerpmann , Steffen Kosinski
IPC分类号： G06F15/16
CPC分类号： H04L41/0863 , G06F11/1438 , G06F11/1443 , G06F2201/82
摘要： An embodiment may include network controller circuitry to be included in a first host computer that includes a host processor to execute an operating system environment. The circuitry may initiate, at least in part, one or more checkpoints of, at least in part, one or more states associated with, at least in part, the operating system environment and network traffic between the first host computer and a second host computer. The circuitry also may coordinate, at least in part, respective execution, at least in part, of the one or more checkpoints with respective execution of one or more other respective checkpoints of the second host computer. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：实施例可以包括要包括在包括主机处理器以执行操作系统环境的第一主计算机中的网络控制器电路。该电路至少部分地可以至少部分地发起与至少部分与第一主计算机和第二主计算机之间的操作系统环境和网络流量相关联的至少一个或多个状态的一个或多个检查点。该电路还可以至少部分地至少部分地协调一个或多个检查点的相应执行，其中相应地执行第二主计算机的一个或多个其他相应的检查点。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

2. 发明申请

US20180188798A1 HYBRID HARDWARE/FIRMWARE POWER MANAGEMENT CONTROLLER FOR MEDIA DEVICES 审中-公开
公开(公告)号：US20180188798A1
公开(公告)日：2018-07-05
申请号：US15396007
申请日：2016-12-30
申请人： Jonathan E. Schmidt , Joerg Hartung , Steffen Kosinski , Jack Cummings
发明人： Jonathan E. Schmidt , Joerg Hartung , Steffen Kosinski , Jack Cummings
IPC分类号： G06F1/32 , G06F13/24 , G06F1/30
摘要： Systems, apparatuses and methods may provide for firmware access wrapper technology that includes a plurality of input registers communicatively coupled to a hardware power controller, a plurality of output registers communicatively coupled to the hardware power controller, and a processor communicatively coupled to the input registers and the output registers. The processor may include configurable logic to identify a control policy change with respect to the hardware power controller, detect input signal information in one or more of the input registers, and conduct a modification of one or more values in the output registers based on the control policy change and the input signal information.

3. 发明申请

US20130246552A1 METHOD AND APPARATUS FOR MANAGING APPLICATION STATE IN A NETWORK INTERFACE CONTROLLER IN A HIGH PERFORMANCE COMPUTING SYSTEM 有权
标题翻译：用于在高性能计算系统中的网络接口控制器中管理应用状态的方法和装置
公开(公告)号：US20130246552A1
公开(公告)日：2013-09-19
申请号：US13989038
申请日：2010-12-09
申请人： Keith D. Underwood , Steffen Kosinski , Jaroslaw Topp , Jan Uerpmann , Michael Redeker
发明人： Keith D. Underwood , Steffen Kosinski , Jaroslaw Topp , Jan Uerpmann , Michael Redeker
IPC分类号： G06F15/167
CPC分类号： H04L45/38 , G06F13/385 , G06F15/167 , H04L1/12 , H04L1/1835 , H04L43/103 , H04L45/60 , H04L47/34 , H04L67/10 , Y02D10/14 , Y02D10/151
摘要： Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.
摘要翻译：提出了与高性能计算系统中节点之间的通信和内部节点之间相关的方法。节点间处理单元与网络控制器接口之间的消息交换处理时间缩短。在网络接口控制器中管理应用程序状态所需的资源被最小化。在网络接口控制器中，多个上下文被复用到一个物理的直接存储器访问引擎中。通过使用多个独立的高速缓存来加速网络接口控制器中的虚拟到物理地址转换，每个级别的页表层次结构缓存在独立的高速缓存中。提供了一种用于在处理单元和网络控制器接口之间分布的数据结构的存储器管理方案。通过将发送序列号空间限制到当前的飞行中消息来减少实现端到端可靠性所需的状态。

4. 发明授权

US10558255B2 Hybrid hardware/firmware power management controller for media devices 有权
公开(公告)号：US10558255B2
公开(公告)日：2020-02-11
申请号：US15396007
申请日：2016-12-30
申请人： Jonathan E. Schmidt , Joerg Hartung , Steffen Kosinski , Jack Cummings
发明人： Jonathan E. Schmidt , Joerg Hartung , Steffen Kosinski , Jack Cummings
IPC分类号： G06F13/32 , G06F1/3287 , G06F13/24 , G06F1/30
摘要： Systems, apparatuses and methods may provide for firmware access wrapper technology that includes a plurality of input registers communicatively coupled to a hardware power controller, a plurality of output registers communicatively coupled to the hardware power controller, and a processor communicatively coupled to the input registers and the output registers. The processor may include configurable logic to identify a control policy change with respect to the hardware power controller, detect input signal information in one or more of the input registers, and conduct a modification of one or more values in the output registers based on the control policy change and the input signal information.

5. 发明申请

US20140189250A1 Store Forwarding for Data Caches 有权
标题翻译：存储转发数据高速缓存
公开(公告)号：US20140189250A1
公开(公告)日：2014-07-03
申请号：US13729945
申请日：2012-12-28
申请人： Steffen Kosinski , Fernando Latorre , Niranjan Cooray , Stanislav Shwartsman , Ethan Kalifon , Varun Mohandru , Pedro Lopez , Tom Aviram-Rosenfeld , Jaroslav Topp , Li-Gao Zei
发明人： Steffen Kosinski , Fernando Latorre , Niranjan Cooray , Stanislav Shwartsman , Ethan Kalifon , Varun Mohandru , Pedro Lopez , Tom Aviram-Rosenfeld , Jaroslav Topp , Li-Gao Zei
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0855 , G06F12/0866
摘要： A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.
摘要翻译：可以使用位或其他向量来识别输入中间缓冲器的地址范围是否对应于与地址范围相关联的最近更新的数据。还可以使用位或其他向量来识别输入中间缓冲器的地址范围是否与要加载的数据的地址范围重叠。然后，处理设备可以完全从中间缓冲区获得要从缓存中完全加载的数据，该中间缓冲器临时缓冲目的地为高速缓存的数据，直到高速缓存准备好接受数据，或者从高速缓存和中间缓冲区取决于特定的向量设置。提供了系统，设备，方法和计算机可读介质。

6. 发明授权

US09436651B2 Method and apparatus for managing application state in a network interface controller in a high performance computing system 有权
标题翻译：用于在高性能计算系统中的网络接口控制器中管理应用状态的方法和装置
公开(公告)号：US09436651B2
公开(公告)日：2016-09-06
申请号：US13989038
申请日：2010-12-09
申请人： Keith D. Underwood , Steffen Kosinski , Jaroslaw Topp , Jan Uerpmann , Michael Redeker
发明人： Keith D. Underwood , Steffen Kosinski , Jaroslaw Topp , Jan Uerpmann , Michael Redeker
IPC分类号： G06F15/16 , G06F15/167 , G06F13/38 , H04L12/773 , H04L12/26
CPC分类号： H04L45/38 , G06F13/385 , G06F15/167 , H04L1/12 , H04L1/1835 , H04L43/103 , H04L45/60 , H04L47/34 , H04L67/10 , Y02D10/14 , Y02D10/151
摘要： Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced. Resources required to manage application state in the network interface controller are minimized. In the network interface controller, multiple contexts are multiplexed into one physical Direct Memory Access engine. Virtual to physical address translation in the network interface controller is accelerated by using a plurality of independent caches, with each level of the page table hierarchy cached in an independent cache. A memory management scheme for data structures distributed between the processing unit and the network controller interface is provided. The state required to implement end-to-end reliability is reduced by limiting the transmit sequence number space to the currently in-flight messages.
摘要翻译：提出了与高性能计算系统中节点之间的通信和内部节点之间相关的方法。节点间处理单元与网络控制器接口之间的消息交换处理时间缩短。在网络接口控制器中管理应用程序状态所需的资源被最小化。在网络接口控制器中，多个上下文被复用到一个物理的直接存储器访问引擎中。通过使用多个独立的高速缓存来加速网络接口控制器中的虚拟到物理地址转换，每个级别的页表层次结构缓存在独立的高速缓存中。提供了一种用于在处理单元和网络控制器接口之间分布的数据结构的存储器管理方案。通过将发送序列号空间限制到当前的飞行中消息来减少实现端到端可靠性所需的状态。

7. 发明申请

US20140189238A1 Two-Level Cache Locking Mechanism 有权
标题翻译：两级缓存锁定机制
公开(公告)号：US20140189238A1
公开(公告)日：2014-07-03
申请号：US13729840
申请日：2012-12-28
申请人： Li-Gao ZEI , Fernando LATORRE , Steffen KOSINSKI , Jaroslaw TOPP , Varun MOHANDRU , Lutz NAETHKE
发明人： Li-Gao ZEI , Fernando LATORRE , Steffen KOSINSKI , Jaroslaw TOPP , Varun MOHANDRU , Lutz NAETHKE
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0864 , G06F12/1063
摘要： A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.
摘要翻译：虚拟标记的高速缓存可以被配置为基于页面偏移值将高速缓存中的虚拟地址条目索引到可锁定集合。当内存操作错过虚拟标记的缓存时，只有一组具有相同页偏移量的虚拟地址条目可能被锁定。此后，可以解除该通用锁定，并且仅锁定与物理地址匹配的物理标签阵列中存储的地址和与物理标签阵列中存储的匹配地址相对应的虚拟标签阵列中的虚拟地址，以减少数量和锁定地址的持续时间。只有当特定的存储器地址请求命中和/或尝试访问锁定集中的一个或多个条目时，才可能停止该机器。提供了设备，系统，方法和计算机可读介质。

8. 发明授权

US08386594B2 Network controller circuitry to initiate, at least in part, one or more checkpoints 有权
标题翻译：网络控制器电路至少部分地启动一个或多个检查点
公开(公告)号：US08386594B2
公开(公告)日：2013-02-26
申请号：US12704240
申请日：2010-02-11
申请人： Keith D. Underwood , David N. Lombard , Jan Uerpmann , Steffen Kosinski
发明人： Keith D. Underwood , David N. Lombard , Jan Uerpmann , Steffen Kosinski
IPC分类号： G06F15/173
CPC分类号： H04L41/0863 , G06F11/1438 , G06F11/1443 , G06F2201/82
摘要： An embodiment may include network controller circuitry to be included in a first host computer that includes a host processor to execute an operating system environment. The circuitry may initiate, at least in part, one or more checkpoints of, at least in part, one or more states associated with, at least in part, the operating system environment and network traffic between the first host computer and a second host computer. The circuitry also may coordinate, at least in part, respective execution, at least in part, of the one or more checkpoints with respective execution of one or more other respective checkpoints of the second host computer. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：实施例可以包括要包括在包括主机处理器以执行操作系统环境的第一主计算机中的网络控制器电路。该电路至少部分地可以至少部分地发起与至少部分与第一主计算机和第二主计算机之间的操作系统环境和网络流量相关联的至少一个或多个状态的一个或多个检查点。该电路还可以至少部分地至少部分地协调一个或多个检查点的相应执行，其中相应地执行第二主计算机的一个或多个其他相应的检查点。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

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