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1. 发明申请

US20140189250A1 Store Forwarding for Data Caches 有权
标题翻译：存储转发数据高速缓存
公开(公告)号：US20140189250A1
公开(公告)日：2014-07-03
申请号：US13729945
申请日：2012-12-28
申请人： Steffen Kosinski , Fernando Latorre , Niranjan Cooray , Stanislav Shwartsman , Ethan Kalifon , Varun Mohandru , Pedro Lopez , Tom Aviram-Rosenfeld , Jaroslav Topp , Li-Gao Zei
发明人： Steffen Kosinski , Fernando Latorre , Niranjan Cooray , Stanislav Shwartsman , Ethan Kalifon , Varun Mohandru , Pedro Lopez , Tom Aviram-Rosenfeld , Jaroslav Topp , Li-Gao Zei
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0855 , G06F12/0866
摘要： A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.
摘要翻译：可以使用位或其他向量来识别输入中间缓冲器的地址范围是否对应于与地址范围相关联的最近更新的数据。还可以使用位或其他向量来识别输入中间缓冲器的地址范围是否与要加载的数据的地址范围重叠。然后，处理设备可以完全从中间缓冲区获得要从缓存中完全加载的数据，该中间缓冲器临时缓冲目的地为高速缓存的数据，直到高速缓存准备好接受数据，或者从高速缓存和中间缓冲区取决于特定的向量设置。提供了系统，设备，方法和计算机可读介质。

2. 发明授权

US09268697B2 Snoop filter having centralized translation circuitry and shadow tag array 有权
标题翻译：具有集中翻译电路和阴影标签阵列的窥探滤波器
公开(公告)号：US09268697B2
公开(公告)日：2016-02-23
申请号：US13730956
申请日：2012-12-29
申请人： Ilan Pardo , Niranjan Cooray , Stanislav Shwartsman , Shlomo Raikin
发明人： Ilan Pardo , Niranjan Cooray , Stanislav Shwartsman , Shlomo Raikin
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0822 , G06F12/0831 , G06F12/1027 , G06F12/1063
摘要： A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.
摘要翻译：描述了包括多个处理核的处理器。处理器包括耦合到每个所述处理核心的互连网络。处理器包括连接到互连网络并与处理器的相干平面逻辑电路相关联的窥探滤波器逻辑电路。监听滤波器逻辑电路包含用于保存信息的电路，该信息不仅识别哪个处理核心缓存由处理核心高速缓存的特定高速缓存线，而且在处理核心的高速缓存中缓存高速缓存行被缓存。

3. 发明申请

US20070150653A1 Processing of cacheable streaming data 审中-公开
标题翻译：可缓存流数据的处理
公开(公告)号：US20070150653A1
公开(公告)日：2007-06-28
申请号：US11315853
申请日：2005-12-22
申请人： Niranjan Cooray , Jack Doweck , Mark Buxton , Varghese George
发明人： Niranjan Cooray , Jack Doweck , Mark Buxton , Varghese George
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0831 , G06F12/0859
摘要： According to one embodiment of the invention, a method is disclosed for receiving a request for cacheable memory type data in a cache-controller in communication with a first cache memory; obtaining the requested data from a first memory device in communication with the first cache memory if the requested data does not resides in at least one of the cache-controller and the first cache memory; allocating a data storage buffer in the cache-controller for storage of the obtained data; and setting the allocated data storage buffer to a streaming data mode if the obtained data is a streaming data to prevent an unrestricted placement of the obtained streaming data into the first cache memory.
摘要翻译：根据本发明的一个实施例，公开了一种用于在与第一高速缓存存储器通信的高速缓存控制器中接收对可缓存存储器类型数据的请求的方法; 如果所请求的数据不驻留在所述高速缓存控制器和所述第一高速缓冲存储器中的至少一个中，则从与所述第一高速缓存存储器通信的第一存储器设备获得所请求的数据; 在所述高速缓存控制器中分配数据存储缓冲器以存储所获得的数据; 以及如果所获得的数据是流数据，则将所分配的数据存储缓冲器设置为流数据模式，以防止所获得的流数据被无限制地放置到第一高速缓冲存储器中。

4. 发明申请

US20190324919A1 Page Tables for Granular Allocation of Memory Pages 审中-公开
公开(公告)号：US20190324919A1
公开(公告)日：2019-10-24
申请号：US16457019
申请日：2019-06-28
申请人： Altug Koker , Ankur Shah , Murali Ramadoss , Niranjan Cooray
发明人： Altug Koker , Ankur Shah , Murali Ramadoss , Niranjan Cooray
IPC分类号： G06F12/1009 , G06F12/1027
摘要： Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.

5. 发明申请

US20050044318A1 Method and apparatus for a trace cache trace-end predictor 失效
标题翻译：跟踪缓存跟踪结果预测器的方法和装置
公开(公告)号：US20050044318A1
公开(公告)日：2005-02-24
申请号：US10646033
申请日：2003-08-22
申请人： Subramaniam Maiyuran , Peter Smith , Niranjan Cooray , Asim Nisar
发明人： Subramaniam Maiyuran , Peter Smith , Niranjan Cooray , Asim Nisar
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F9/3808
摘要： A method and apparatus for a trace end predictor for a trace cache is disclosed. In one embodiment, the trace end predictor may have one or more buffers to contain a head address for a subsequent trace. The head address may include the way number and set number of the next head, along with partial stew data to support additional execution predictors. The buffers may also include tag data of the current trace's tail address, and may additionally include control bits for determining whether to replace the buffer's contents with information from another trace's tail. Reading the next head address from the trace end predictor, as opposed to reading it from the trace cache array, may reduce certain execution time delays.
摘要翻译：公开了一种用于跟踪高速缓存的跟踪结束预测器的方法和装置。在一个实施例中，跟踪结束预测器可以具有一个或多个缓冲器以包含后续跟踪的头地址。头部地址可以包括下一个头部的路径编号和编号，以及部分炖菜数据以支持附加的执行预测器。缓冲器还可以包括当前迹线的尾部地址的标签数据，并且还可以包括用于确定是否用来自另一跟踪尾部的信息替换缓冲器内容的控制位。从跟踪结束预测器读取下一个头地址，而不是从跟踪高速缓存阵列读取它，可能会减少某些执行时间延迟。

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