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1. 发明申请

US20140189238A1 Two-Level Cache Locking Mechanism 有权
标题翻译：两级缓存锁定机制
公开(公告)号：US20140189238A1
公开(公告)日：2014-07-03
申请号：US13729840
申请日：2012-12-28
申请人： Li-Gao ZEI , Fernando LATORRE , Steffen KOSINSKI , Jaroslaw TOPP , Varun MOHANDRU , Lutz NAETHKE
发明人： Li-Gao ZEI , Fernando LATORRE , Steffen KOSINSKI , Jaroslaw TOPP , Varun MOHANDRU , Lutz NAETHKE
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0864 , G06F12/1063
摘要： A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.
摘要翻译：虚拟标记的高速缓存可以被配置为基于页面偏移值将高速缓存中的虚拟地址条目索引到可锁定集合。当内存操作错过虚拟标记的缓存时，只有一组具有相同页偏移量的虚拟地址条目可能被锁定。此后，可以解除该通用锁定，并且仅锁定与物理地址匹配的物理标签阵列中存储的地址和与物理标签阵列中存储的匹配地址相对应的虚拟标签阵列中的虚拟地址，以减少数量和锁定地址的持续时间。只有当特定的存储器地址请求命中和/或尝试访问锁定集中的一个或多个条目时，才可能停止该机器。提供了设备，系统，方法和计算机可读介质。

2. 发明申请

US20140189253A1 CACHE COHERENCY AND PROCESSOR CONSISTENCY 有权
标题翻译：高速缓存处理器一致
公开(公告)号：US20140189253A1
公开(公告)日：2014-07-03
申请号：US13729629
申请日：2012-12-28
申请人： Varun K. MOHANDRU , Fernando LATORRE , Li-Gao ZEI , Allan D. KNIES , Rami MAY , Lutz NAETHKE
发明人： Varun K. MOHANDRU , Fernando LATORRE , Li-Gao ZEI , Allan D. KNIES , Rami MAY , Lutz NAETHKE
IPC分类号： G06F12/08
CPC分类号： G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F12/0815 , G06F2212/507
摘要： Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.
摘要翻译：响应于在当前翻译窗口中执行计算机指令，可以修改与为执行访问的高速缓存行相关联的状态指示符。状态指示符可以包括：第一指示符，用于指示计算机指令是否是从后续转换窗口移动到当前转换窗口的加载指令;第二指示符，用于指示高速缓存行是否在缓存中被修改，响应于执行计算机指令，第三指示符，用于指示高速缓存行是否响应于计算机指令的执行在高速缓存中被推测地修改;第四指示符，用于指示高速缓存行是否被计算机指令推测性加载;第五指示符，用于指示执行计算机指令的核心是否独占拥有高速缓存行，以及指示高速缓存行是否无效的第六指示符。

3. 发明申请

US20130262793A1 SPLIT-WORD MEMORY 有权
标题翻译：分词记忆
公开(公告)号：US20130262793A1
公开(公告)日：2013-10-03
申请号：US13436745
申请日：2012-03-30
申请人： Lutz NAETHKE , Axel BORKOWSKI , Bert BRETSCHNEIDER , Kyriakos A. STAVROU , Rainer THEUER
发明人： Lutz NAETHKE , Axel BORKOWSKI , Bert BRETSCHNEIDER , Kyriakos A. STAVROU , Rainer THEUER
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30185 , G06F9/30192 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3887 , G06F9/3889 , G06F12/00 , G06F12/04 , G06F12/0607 , G06F12/0846 , G06F12/0862 , G06F12/0875 , G06F15/7807 , G06F15/7857 , G06F2212/452 , G06F2212/6028 , Y02D10/12 , Y02D10/13
摘要： Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.
摘要翻译：有效地存储，读取和/或处理单词数据音节的方法，过程和装置。包括多个音节的数据字的一部分可以被计算机处理器读取。处理器可以从第一存储器读取数据字的第一个音节。处理器可以从存储器的第二部分读取数据字的第二个音节。第二个音节可以包括比第一个音节的位不太关键的比特。第二存储器可以基于一个或多个物理属性与第一存储器不同。

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