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1. 发明授权

US08260837B2 Handling denormal floating point operands when result must be normalized 失效
标题翻译：当结果必须归一化时，处理非正常浮点操作数
公开(公告)号：US08260837B2
公开(公告)日：2012-09-04
申请号：US12234890
申请日：2008-09-22
申请人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
发明人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
IPC分类号： G06F7/487
CPC分类号： G06F7/483 , G06F7/49936
摘要： A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.
摘要翻译：当结果必须归一化时，用于处理异常浮点运算的系统。操作数B（opB）上的前导零计数器（lzc）用于在opB为非正常时限制对准偏移，但是远大于操作数A和C的乘积即AC。通过在标准化期间限制B的附加偏移，通过opB中的前导零的数量，在对准移位器的输出总线中不需要增加。此外，附加移位可以在对准移位器中进行，或者延迟到流水线中的后一阶段，其中结果被归一化。

2. 发明授权

US08144708B1 Collaborative multicast routing (CMR) for multicasting in unidirectional, hybrid, multi-tiered mobile wireless network 有权
标题翻译：用于在单向，混合，多层移动无线网络中组播的协作多播路由（CMR）
公开(公告)号：US08144708B1
公开(公告)日：2012-03-27
申请号：US12592687
申请日：2009-11-30
申请人： Mohiuddin Ahmed , Son Dao , Noparut Vanitchanant
发明人： Mohiuddin Ahmed , Son Dao , Noparut Vanitchanant
IPC分类号： H04L12/28
CPC分类号： H04L12/1877 , H04L45/00 , H04L45/026 , H04L45/16 , H04W40/02
摘要： The present invention provides a scalable and reliable collaborative multicast routing for multicasting in hybrid, multi-tiered, mobile heterogeneous wireless networks. It establishes a multicast tree, maintains the established route, detects and prevents most link breakage within the multicast tree by a neighboring node or the cooperation of the neighboring node, and enables merging of partitioned multicast trees of the same multicast group by nodes that participate in one of the partitioned multicast trees. The use of local nodes to collaboratively establish, maintain, recover, and merge the hybrid, multi-tiered mobile wireless networks that use heterogeneous set of mobile wireless nodes is the fundamental basis for the collaborative multicast routing scheme of the present invention.
摘要翻译：本发明提供了一种可扩展和可靠的协作多播路由，用于在混合多层移动异构无线网络中进行多播。建立组播树，维护已建立的路由，通过邻居节点检测和防止组播树内的大多数链路断裂或相邻节点的协作，使得能够通过参与节点的节点合并同一组播组的分区组播树一个分区的多播树。使用本地节点协同建立，维护，恢复和合并使用异构移动无线节点的混合多层移动无线网络是本发明的协同多播路由方案的基础。

3. 发明申请

US20090077152A1 Handling Denormal Floating Point Operands When Result Must be Normalized 失效
标题翻译：当结果必须归一化时，处理非正常浮点操作数
公开(公告)号：US20090077152A1
公开(公告)日：2009-03-19
申请号：US12234890
申请日：2008-09-22
申请人： Lawrence Joseph Powell, JR. , Martin Stanley Schmookler , Son Dao Trong
发明人： Lawrence Joseph Powell, JR. , Martin Stanley Schmookler , Son Dao Trong
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49936
摘要： A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.
摘要翻译：当结果必须归一化时，用于处理异常浮点运算的系统。操作数B（opB）上的前导零计数器（lzc）用于在opB为非正常时限制对准偏移，但是远大于操作数A和C的乘积即AC。通过在标准化期间限制B的附加偏移，通过opB中的前导零的数量，在对准移位器的输出总线中不需要增加。此外，附加移位可以在对准移位器中进行，或者延迟到流水线中的后一阶段，其中结果被归一化。

4. 发明授权

US07451172B2 Handling denormal floating point operands when result must be normalized 失效
标题翻译：当结果必须归一化时，处理非正常浮点操作数
公开(公告)号：US07451172B2
公开(公告)日：2008-11-11
申请号：US11055046
申请日：2005-02-10
申请人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
发明人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49936
摘要： A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.
摘要翻译：当结果必须被归一化时，用于处理异常浮点操作数的方法。操作数B（opB）上的前导零计数器（lzc）用于在opB为非正常时限制对准偏移，但是远大于操作数A和C的乘积即AC。通过在标准化期间限制B的附加偏移，通过opB中的前导零的数量，在对准移位器的输出总线中不需要增加。此外，附加移位可以在对准移位器中进行，或者延迟到流水线中的后一阶段，其中结果被归一化。

5. 发明申请

US20060179100A1 System and method for performing floating point store folding 失效
标题翻译：执行浮点存储折叠的系统和方法
公开(公告)号：US20060179100A1
公开(公告)日：2006-08-10
申请号：US11054686
申请日：2005-02-09
申请人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
发明人： Juergen Haess , Michael Kroener , Dung Nguyen , Lawrence Powell , Eric Schwarz , Son Dao-Trong , Raymond Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3826 , G06F9/30014 , G06F9/3824 , G06F9/3838 , G06F9/3885
摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.
摘要翻译：一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

6. 发明授权

US06681313B1 Method and system for fast access to a translation lookaside buffer 失效
标题翻译：用于快速访问翻译后备缓冲区的方法和系统
公开(公告)号：US06681313B1
公开(公告)日：2004-01-20
申请号：US09566319
申请日：2000-05-08
申请人： Son Dao Trong , Luis Parga Cacheiro , Rolf Sautter , Hans-Werner Tast
发明人： Son Dao Trong , Luis Parga Cacheiro , Rolf Sautter , Hans-Werner Tast
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： In a system for conducting virtual address translation in a virtual memory system and implementing a table such as a Translation Lookaside Buffer, a system and method enabling quicker access to tables entries in which the entries are addressed after adding a plurality of address parts wherein the plurality is two (2) or (3). Particularly, a smaller and/or faster adder is used having, for example, only n=2 ports in the time critical path. In order to make the exact address calculation, during array accesses, a multiplexor is implemented to decide, after the TLB arrays are accessed for preselection, which of a plurality of possible entries has to be taken.
摘要翻译：在用于在虚拟存储器系统中进行虚拟地址转换并实现诸如翻译后备缓冲器之类的表的系统中，能够更快地访问在其中条目被寻址的表条目的系统和方法，其中添加了多个地址部分，其中多个是二（2）或（3）。特别地，使用较小和/或更快的加法器，其具有例如在时间关键路径中仅n = 2个端口。为了进行精确的地址计算，在阵列访问期间，实现多路复用器以在对预选择的TLB阵列进行访问之后决定必须采取多个可能的条目中的哪一个。

7. 发明授权

US5070471A High speed multiplier which divides multiplying factor into parts and adds partial end products 失效
标题翻译：高倍数乘法器将乘法因子分为零件和部分最终产品
公开(公告)号：US5070471A
公开(公告)日：1991-12-03
申请号：US478283
申请日：1990-02-09
申请人： Son Dao-Trong , Klaus J. Getzlaff , Klaus Helwig
发明人： Son Dao-Trong , Klaus J. Getzlaff , Klaus Helwig
IPC分类号： G06F7/533 , G06F7/52 , G06F7/53
CPC分类号： G06F7/5324 , G06F7/5338
摘要： A multiplier for multiplying two binary operands is presented which comprises an encoding unit, a multiplying unit composed of two multiplying arrays, and a logic unit. The encoding unit to which the second operand is applied generates factors following the Booth algorithm. The two multiplying arrays are respectively applied with the first operand as well as with factors belonging to the higher significance digits or the lower significance digits, respectively, of the second operand. In both multiplying arrays the multiplication of the factors with the first operand into a respective partial end product is simultaneously performed. Both partial end products are applied to the logic unit which generates therefrom the end product in accordance with the algorithm used at the beginning.
摘要翻译：提出了用于乘以两个二进制操作数的乘法器，其包括编码单元，由两个乘法阵列组成的乘法单元和逻辑单元。应用第二个操作数的编码单元生成遵循布斯算法的因子。两个相乘阵列分别与第一操作数一起使用，以及分别属于第二操作数的较高有效数字或较低有效数字的因子。在两个乘法阵列中，同时执行将因子与第一操作数相乘到相应的部分最终乘积中。两个部分终端产品都被应用于逻辑单元，该逻辑单元根据开始时使用的算法生成最终产品。

8. 发明授权

US07461117B2 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准偏移量计算指示mo的选择信号对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。

9. 发明授权

US5912453A Multiple application chip card with decoupled programs 失效
标题翻译：具有解耦程序的多应用芯片卡
公开(公告)号：US5912453A
公开(公告)日：1999-06-15
申请号：US720162
申请日：1996-09-25
申请人： Klaus Gungl , Son Dao Trong
发明人： Klaus Gungl , Son Dao Trong
IPC分类号： G06F12/14 , G06F21/02 , G06F21/24 , G06K17/00 , G06K19/07 , G06K19/073 , G07F7/10 , G11C5/00 , G06K19/00
CPC分类号： G07F7/1008 , G06F12/145 , G06K19/072 , G06Q20/341 , G06Q20/35765
摘要： The integration of multiple application programs on one chip card is described, whereby the application programs stored on it do not have access to each other, which is achieved through a separation and de-coupling of the individual programs from one another. A first embodiment has several mutually-independent units, consisting respectively of a processor unit and a memory unit. Communication of these independent units with the external world and also with each other takes place through a control unit. A communication of the independent units with each other can only take place through the respective processor units, so that the linked memory units may not be accessed by circumvention of the processor unit. In a further embodiment, the separation of different applications on a chip card with only one processor takes place through the insertion of a separation of the application segments in the memory area of the chip card. The separation has as a result that each application may only access one predetermined area within the memory, and that access outside of the specified memory area is disabled for this application.
摘要翻译：描述了将多个应用程序集成在单个芯片卡上，由此存储在其上的应用程序不能彼此访问，这通过各个程序彼此的分离和解耦来实现。第一实施例具有分别由处理器单元和存储器单元组成的若干相互独立的单元。这些独立单位与外部世界的交流，也是通过控制单元进行的。独立单元彼此的通信只能通过相应的处理器单元进行，从而通过规避处理器单元可能不能访问所链接的存储器单元。在另一实施例中，通过在芯片卡的存储器区域中插入应用程序段的分离，仅在一个处理器的芯片卡上分离不同的应用程序。结果是，每个应用程序只能访问存储器内的一个预定区域，并且对该应用程序禁用对指定存储器区域之外的访问。

10. 发明授权

US5517438A Fast multiply-add instruction sequence in a pipeline floating-point processor 失效
标题翻译：快速乘法加法指令序列在流水线浮点处理器中
公开(公告)号：US5517438A
公开(公告)日：1996-05-14
申请号：US278522
申请日：1994-07-20
申请人： Son Dao-Trong , Juergen Haas , Rolf Mueller
发明人： Son Dao-Trong , Juergen Haas , Rolf Mueller
IPC分类号： G06F9/38 , G06F7/00 , G06F7/487 , G06F7/508 , G06F7/527 , G06F7/53 , G06F7/533 , G06F7/544 , G06F7/76 , G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884 , G06F7/483
摘要： A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).
摘要翻译：一种流水线浮点处理器，其中重新组合加法流水线，使得当加法使用紧前相关乘法的结果（快速乘法指令）时，不需要等待周期。重组意味着流水线浮动处理器的现有数据流的以下改变：经由来自乘法器M的归一化数据的路径ND的数据反馈到对准器AL1和AL2; 考虑到产品的可能的前导零位，并且通过Z1和Z2对潜在的保护数字进行特殊归零，在数据路径的两侧左移一位数字特征; 指数由9位构成，用于溢出和下溢识别，并且由于下溢，指数结果将通过真零单位（T / C）在运行中复位为零。

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