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1. 发明授权

US08260837B2 Handling denormal floating point operands when result must be normalized 失效
标题翻译：当结果必须归一化时，处理非正常浮点操作数
公开(公告)号：US08260837B2
公开(公告)日：2012-09-04
申请号：US12234890
申请日：2008-09-22
申请人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
发明人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
IPC分类号： G06F7/487
CPC分类号： G06F7/483 , G06F7/49936
摘要： A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.
摘要翻译：当结果必须归一化时，用于处理异常浮点运算的系统。操作数B（opB）上的前导零计数器（lzc）用于在opB为非正常时限制对准偏移，但是远大于操作数A和C的乘积即AC。通过在标准化期间限制B的附加偏移，通过opB中的前导零的数量，在对准移位器的输出总线中不需要增加。此外，附加移位可以在对准移位器中进行，或者延迟到流水线中的后一阶段，其中结果被归一化。

2. 发明申请

US20090077152A1 Handling Denormal Floating Point Operands When Result Must be Normalized 失效
标题翻译：当结果必须归一化时，处理非正常浮点操作数
公开(公告)号：US20090077152A1
公开(公告)日：2009-03-19
申请号：US12234890
申请日：2008-09-22
申请人： Lawrence Joseph Powell, JR. , Martin Stanley Schmookler , Son Dao Trong
发明人： Lawrence Joseph Powell, JR. , Martin Stanley Schmookler , Son Dao Trong
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49936
摘要： A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.
摘要翻译：当结果必须归一化时，用于处理异常浮点运算的系统。操作数B（opB）上的前导零计数器（lzc）用于在opB为非正常时限制对准偏移，但是远大于操作数A和C的乘积即AC。通过在标准化期间限制B的附加偏移，通过opB中的前导零的数量，在对准移位器的输出总线中不需要增加。此外，附加移位可以在对准移位器中进行，或者延迟到流水线中的后一阶段，其中结果被归一化。

3. 发明授权

US07451172B2 Handling denormal floating point operands when result must be normalized 失效
标题翻译：当结果必须归一化时，处理非正常浮点操作数
公开(公告)号：US07451172B2
公开(公告)日：2008-11-11
申请号：US11055046
申请日：2005-02-10
申请人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
发明人： Lawrence Joseph Powell, Jr. , Martin Stanley Schmookler , Son Dao Trong
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49936
摘要： A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.
摘要翻译：当结果必须被归一化时，用于处理异常浮点操作数的方法。操作数B（opB）上的前导零计数器（lzc）用于在opB为非正常时限制对准偏移，但是远大于操作数A和C的乘积即AC。通过在标准化期间限制B的附加偏移，通过opB中的前导零的数量，在对准移位器的输出总线中不需要增加。此外，附加移位可以在对准移位器中进行，或者延迟到流水线中的后一阶段，其中结果被归一化。

4. 发明授权

US5875123A Carry-select adder with pre-counting of leading zero digits 失效
标题翻译：进位选择加法器，前置零位预计数
公开(公告)号：US5875123A
公开(公告)日：1999-02-23
申请号：US765419
申请日：1997-05-13
申请人： Son Dao Trong , Gunter Gerwig , Klaus Getzlaff , Wilhelm Haller
发明人： Son Dao Trong , Gunter Gerwig , Klaus Getzlaff , Wilhelm Haller
IPC分类号： G06F7/485 , G06F7/00 , G06F7/50 , G06F7/507 , G06F7/74 , G06F7/42
CPC分类号： G06F7/74 , G06F7/485
摘要： A method and apparatus for the determination of leading zero digits of a sum is presented herein. The technique incorporates the parallel determination of partial sums of single digits accounting for the possibility of carries and on the basis thereof the pre-determination of potential zero digits or potential leading zero digits. Upon the establishment of a correct partial sum, the potential zero digits are selected and evaluated thereby determining the leading zero digits. The invention may be implemented in an adder in parallel or via a hierarchical structure. The parallelism permits time-savings in the determination of a normalized sum. The invention is preferably incorporated into adders, floating point computing units and/or data processing units.
摘要翻译： PCT No.PCT / EP95 / 01455 Sec。 371日期1997年5月13日 102（e）日期1997年5月13日PCT提交1995年4月18日PCT公布。公开号WO96 / 33456 日期1996年10月24日本文给出了用于确定和的前导零数字的方法和装置。该技术包含了对携带可能性的单位数部分和的并行确定，并且在此基础上预先确定了潜在的零位或潜在的前导零位。在建立正确的部分和时，选择和评估潜在的零数字，从而确定前导零数字。本发明可以并行地或通过分层结构在加法器中实现。并行性允许在确定归一化总和时节省时间。本发明优选地结合到加法器，浮点计算单元和/或数据处理单元中。

5. 发明授权

US07461117B2 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US07461117B2
公开(公告)日：2008-12-02
申请号：US11055812
申请日：2005-02-11
申请人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Dao Trong , Juergen Haess , Christian Jacobi , Klaus Michael Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准偏移量计算指示mo的选择信号对准逻辑（3）输出的高有效位具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6）的阶段。

6. 发明授权

US5912453A Multiple application chip card with decoupled programs 失效
标题翻译：具有解耦程序的多应用芯片卡
公开(公告)号：US5912453A
公开(公告)日：1999-06-15
申请号：US720162
申请日：1996-09-25
申请人： Klaus Gungl , Son Dao Trong
发明人： Klaus Gungl , Son Dao Trong
IPC分类号： G06F12/14 , G06F21/02 , G06F21/24 , G06K17/00 , G06K19/07 , G06K19/073 , G07F7/10 , G11C5/00 , G06K19/00
CPC分类号： G07F7/1008 , G06F12/145 , G06K19/072 , G06Q20/341 , G06Q20/35765
摘要： The integration of multiple application programs on one chip card is described, whereby the application programs stored on it do not have access to each other, which is achieved through a separation and de-coupling of the individual programs from one another. A first embodiment has several mutually-independent units, consisting respectively of a processor unit and a memory unit. Communication of these independent units with the external world and also with each other takes place through a control unit. A communication of the independent units with each other can only take place through the respective processor units, so that the linked memory units may not be accessed by circumvention of the processor unit. In a further embodiment, the separation of different applications on a chip card with only one processor takes place through the insertion of a separation of the application segments in the memory area of the chip card. The separation has as a result that each application may only access one predetermined area within the memory, and that access outside of the specified memory area is disabled for this application.
摘要翻译：描述了将多个应用程序集成在单个芯片卡上，由此存储在其上的应用程序不能彼此访问，这通过各个程序彼此的分离和解耦来实现。第一实施例具有分别由处理器单元和存储器单元组成的若干相互独立的单元。这些独立单位与外部世界的交流，也是通过控制单元进行的。独立单元彼此的通信只能通过相应的处理器单元进行，从而通过规避处理器单元可能不能访问所链接的存储器单元。在另一实施例中，通过在芯片卡的存储器区域中插入应用程序段的分离，仅在一个处理器的芯片卡上分离不同的应用程序。结果是，每个应用程序只能访问存储器内的一个预定区域，并且对该应用程序禁用对指定存储器区域之外的访问。

7. 发明授权

US5363321A Digital circuit for calculating a logarithm of a number 失效
标题翻译：用于计算数字对数的数字电路
公开(公告)号：US5363321A
公开(公告)日：1994-11-08
申请号：US69954
申请日：1993-05-28
申请人： Son Dao Trong , Klaus Helwig , Markus Loch
发明人： Son Dao Trong , Klaus Helwig , Markus Loch
IPC分类号： G06F7/556 , G06F7/00
CPC分类号： G06F7/556
摘要： A digital circuit computes the logarithm of a number. The circuit makes the computation by first determining a multiplicity of factors f.sub.i from a predetermined set of factors such that the product of the multiplicity of factors f.sub.i and the number equals the base of the logarithm. A memory stores the logarithms of all the numbers in the predetermined set. The circuit then looks-up and sums the logarithms of the multiplicity of factors f.sub.i, and then subtracts the sum from one to yield the logarithm of the number.
摘要翻译：数字电路计算一个数字的对数。该电路通过首先从预定因子集合确定多项因子fi使得计算，使得多项因子f i和数量的乘积等于对数的基数。存储器存储预定集合中所有数字的对数。然后，电路查找并求和多项因子fi的对数，然后从一个减去总和以产生数字的对数。

8. 发明授权

US08244783B2 Normalizer shift prediction for log estimate instructions 失效
标题翻译：用于对数估计指令的归一化器偏移预测
公开(公告)号：US08244783B2
公开(公告)日：2012-08-14
申请号：US12208439
申请日：2008-09-11
申请人： Maarten J. Boersma , Michael Klein , Jochen Preiss , Son Dao Trong
发明人： Maarten J. Boersma , Michael Klein , Jochen Preiss , Son Dao Trong
IPC分类号： G06F5/01
CPC分类号： G06F7/74
摘要： A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction.
摘要翻译：浮点处理器单元包括在浮点单元的归一化部分内的移位量计算电路，其中移位量计算电路用于计算作为可流水线指令运行的对数估计指令的归一化器移位量。

9. 发明授权

US07716266B2 Common shift-amount calculation for binary and hex floating point 失效
标题翻译：二进制和十六进制浮点的通用移位量计算
公开(公告)号：US07716266B2
公开(公告)日：2010-05-11
申请号：US11341256
申请日：2006-01-26
申请人： Son Dao Trong , Juergen Haess , Klaus Michael Kroener , Eric M. Schwarz
发明人： Son Dao Trong , Juergen Haess , Klaus Michael Kroener , Eric M. Schwarz
IPC分类号： G06F7/38 , G06F7/50 , G06F7/52
CPC分类号： G06F7/483 , G06F7/5443 , G06F2207/3812
摘要： A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC−expB+CV).
摘要翻译：一种用于执行二进制模式和十六进制模式的方法和系统根据公式A * C + B在浮点算术单元中乘法 - 浮点运算，其中A，B和C操作数各自具有分数和指数部分expA ，expB和expC和乘积A * C的指数被计算，并且与包含专用于使用无符号偏移指数的指数偏差值的加数指数进行比较，其中比较产生用于将加数与产品操作数，其中移位量计算根据公式（expA + expC-expB + CV）为二进制和十六进制提供公共值CV。

10. 发明申请

US20100063985A1 NORMALIZER SHIFT PREDICTION FOR LOG ESTIMATE INSTRUCTIONS 失效
标题翻译：用于日志估计指令的正则化移位预测
公开(公告)号：US20100063985A1
公开(公告)日：2010-03-11
申请号：US12208439
申请日：2008-09-11
申请人： Maarten J. Boersma , Michael Klein , Jochen Preiss , Son Dao Trong
发明人： Maarten J. Boersma , Michael Klein , Jochen Preiss , Son Dao Trong
IPC分类号： G06F7/00
CPC分类号： G06F7/74
摘要： A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction.
摘要翻译：浮点处理器单元包括在浮点单元的归一化部分内的移位量计算电路，其中移位量计算电路用于计算作为可流水线指令运行的对数估计指令的归一化器移位量。

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