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1. 发明授权

US08927365B2 Method of eDRAM DT strap formation in FinFET device structure 有权
标题翻译： FinFET器件结构中eDRAM DT带形成方法
公开(公告)号：US08927365B2
公开(公告)日：2015-01-06
申请号：US13556437
申请日：2012-07-24
申请人： Veeraraghavan S. Basker , Sivananda Kanakasabapathy , Tenko Yamashita , Chun-Chen Yeb
发明人： Veeraraghavan S. Basker , Sivananda Kanakasabapathy , Tenko Yamashita , Chun-Chen Yeb
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10826 , H01L27/1087 , H01L27/10879 , H01L27/1211
摘要： The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.
摘要翻译：说明书和附图提出了一种新的方法，设备和计算机/软件相关产品（例如，计算机可读存储器），用于实现Fin FET器件结构中的eDRAM带形成。提供了在第一半导体层和第二半导体层之间至少包括绝缘体层的半导体绝缘体（SOI）衬底。（金属）带形成是通过在第二半导体层（Si）的鳍部分上沉积导电层和延伸到第二半导体层的每个DT电容器中的半导体材料（多晶硅）来实现的。金属带由氮化物间隔物密封，以防止PWL和DT电容器之间的短路。

2. 发明授权

US08673165B2 Sidewall image transfer process with multiple critical dimensions 有权
标题翻译：具有多个关键尺寸的侧壁图像传输过程
公开(公告)号：US08673165B2
公开(公告)日：2014-03-18
申请号：US13267198
申请日：2011-10-06
申请人： Sudharshanan Raghunathan , Sivananda Kanakasabapathy , Ryan O. Jung , Allen H Gabor , Sean D. Burns , Erin Catherine McLellan
发明人： Sudharshanan Raghunathan , Sivananda Kanakasabapathy , Ryan O. Jung , Allen H Gabor , Sean D. Burns , Erin Catherine McLellan
IPC分类号： H01L21/311
CPC分类号： H01L21/0338 , H01L21/0337
摘要： Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.
摘要翻译：本发明的实施例提供了一种在具有多个关键尺寸的侧壁图像转印工艺中形成半导体器件的方法。该方法包括在多个心轴上形成多层介质层，多层介质层具有覆盖多个心轴的多个区域，多层介质层的多个区域具有不同的厚度; 通过施加定向蚀刻工艺将多层电介质层的多个区域蚀刻成间隔物，间隔物形成在多个心轴的侧壁旁边，并且具有对应于多个区域的多个区域的不同厚度的不同宽度电介质层; 去除间隔件之间的多个心轴; 并将间隔物的底部图像转移到间隔物下面的一个或多个层中。

3. 发明授权

US08586478B2 Method of making a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08586478B2
公开(公告)日：2013-11-19
申请号：US13424932
申请日：2012-03-20
申请人： Eiichi Soda , Yunpeng Yin , Sivananda Kanakasabapathy
发明人： Eiichi Soda , Yunpeng Yin , Sivananda Kanakasabapathy
IPC分类号： H01L21/44
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.
摘要翻译：在半导体器件中制造具有自对准通孔的互连结构的改进方法利用侧壁图像转移来限定沟槽图案。在蚀刻通孔和随后蚀刻沟槽期间，侧壁高度用作牺牲掩模，使得下面的金属硬掩模被保护。因此可以利用更薄的硬掩模和/或更广泛的蚀刻化学物质。

4. 发明申请

US20130178022A1 METHOD FOR FABRICATING TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开
标题翻译：用于制作具有残留通道和放大源/漏极的晶体管的方法
公开(公告)号：US20130178022A1
公开(公告)日：2013-07-11
申请号：US13618186
申请日：2012-09-14
申请人： Kangguo CHENG , Ali KHAKIFIROOZ , Sivananda KANAKASABAPATHY , Pranita KULKARNI , Balasubramanian S. HARAN
发明人： Kangguo CHENG , Ali KHAKIFIROOZ , Sivananda KANAKASABAPATHY , Pranita KULKARNI , Balasubramanian S. HARAN
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/7848 , H01L29/785
摘要： A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer.
摘要翻译：提供了一种用于制造晶体管的方法。根据该方法，在第一半导体层上形成第二半导体层，在第二半导体层上形成虚拟栅极结构。栅极间隔件形成在虚拟栅极结构的侧壁上，并且去除虚拟栅极结构以形成空腔。除去腔下方的第二半导体层。栅电介质形成在第一半导体层的第一部分上并且邻近第二半导体层的侧壁和栅极间隔物的侧壁。栅极导体形成在栅极电介质的第一部分上并邻接栅极电介质的第二部分。凸起的源/漏区形成在第二半导体层中，其中至少部分凸起的源极/漏极区在栅极间隔物之下。

5. 发明申请

US20110212548A1 METHOD FOR SEMICONDUCTOR GATE HARDMASK REMOVAL AND DECOUPLING OF IMPLANTS 有权
标题翻译：用于半导体闸门去除和去除植入物的方法
公开(公告)号：US20110212548A1
公开(公告)日：2011-09-01
申请号：US12714702
申请日：2010-03-01
申请人： SIVANANDA KANAKASABAPATHY , HEMANTH JAGANNATHAN
发明人： SIVANANDA KANAKASABAPATHY , HEMANTH JAGANNATHAN
IPC分类号： H01L21/336 , H01L21/66
CPC分类号： H01L29/4908 , H01L29/66772
摘要： A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.
摘要翻译：提供了一种用于制造具有注入的源极/漏极区域和栅极区域的半导体器件的方法，栅极区域在源极/漏极注入期间被栅极硬掩模掩蔽，栅极区域具有分层在金属上的金属上的多晶硅栅极高K电介质层。栅极区域和源极/漏极区域可以用膜上的自平面旋转覆盖。该膜可以被覆盖回蚀刻以露出栅极硬掩模，同时保持在植入的源极/漏极区域上的膜上的回蚀刻自平坦化自旋。栅极硬掩模可以被蚀刻回来，同时蚀刻的后膜保持在适当位置以保护植入的源极/漏极区域。栅极区域可以是低能量注入以降低多晶硅层的薄层电阻。然后可以去除蚀刻后的膜。

6. 发明申请

US20090279354A1 Stacked Magnetic Devices 失效
标题翻译：堆叠式磁性器件
公开(公告)号：US20090279354A1
公开(公告)日：2009-11-12
申请号：US12504860
申请日：2009-07-17
申请人： Sivananda Kanakasabapathy , Yu Lu , Michael Christopher Gaidis, III
发明人： Sivananda Kanakasabapathy , Yu Lu , Michael Christopher Gaidis, III
IPC分类号： G11C11/14
CPC分类号： G11C11/15
摘要： Techniques for improving magnetic device performance are provided. In one aspect, a magnetic device, e.g., a magnetic random access memory device, is provided which comprises a plurality of current carrying lines; and two or more adjacent stacked magnetic toggling devices sharing at least one of the plurality of current carrying lines in common and positioned therebetween. The magnetic device is configured such that at least one of the adjacent magnetic toggling devices toggles mutually exclusively of another of the adjacent magnetic toggling devices. In an exemplary embodiment, the magnetic device comprises a plurality of levels with each of the adjacent stacked magnetic toggling devices residing in a different level.
摘要翻译：提供了提高磁性器件性能的技术。在一个方面，提供一种磁性装置，例如磁性随机存取存储装置，其包括多个载流线; 以及两个或更多个相邻的层叠磁性切换装置，其共同地共享多个载流线中的至少一个并且位于它们之间。磁性装置被配置成使得至少一个相邻的磁性切换装置互相切换另一个相邻的磁性切换装置。在示例性实施例中，磁性装置包括多个级别，其中每个相邻的层叠磁性切换装置处于不同的水平。

7. 发明申请

US20070166840A1 Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权
标题翻译：利用侧壁间隔物特征在集成电路中形成磁隧道结
公开(公告)号：US20070166840A1
公开(公告)日：2007-07-19
申请号：US11333997
申请日：2006-01-18
申请人： Solomon Assefa , Michael Gaidis , Sivananda Kanakasabapathy , John Hummel , David Abraham
发明人： Solomon Assefa , Michael Gaidis , Sivananda Kanakasabapathy , John Hummel , David Abraham
IPC分类号： H01L21/00 , H01L29/94
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译：描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

8. 发明申请

US20130005129A1 STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET 有权
标题翻译：用FINFET整合嵌入式DRAM的结构和方法
公开(公告)号：US20130005129A1
公开(公告)日：2013-01-03
申请号：US13612069
申请日：2012-09-12
申请人： Sivananda KANAKASABAPATHY , Hemanth JAGANNATHAN , Geng WANG
发明人： Sivananda KANAKASABAPATHY , Hemanth JAGANNATHAN , Geng WANG
IPC分类号： H01L21/283
CPC分类号： H01L27/10826 , H01L21/26586 , H01L21/845 , H01L27/10879 , H01L27/10891 , H01L27/1211
摘要： Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap.
摘要翻译：各种实施例将嵌入式动态随机存取存储器与鳍式场效应晶体管集成。在一个实施例中，在衬底上形成第一鳍结构和至少第二鳍结构。在第一和第二翅片结构之间形成深沟槽区域。在深沟槽区域内形成高k金属栅极。高k金属栅极包括高k电介质层和金属层。多晶硅材料沉积在与金属层相邻的深沟槽区域内。高k金属栅极和多晶硅材料被凹入并蚀刻到衬底绝缘体层的顶表面下方的区域。在深沟槽区域中形成多晶带。该多晶带的尺寸设计成在第一和第二鳍结构的顶表面下方。第一和第二翅片结构电耦合到多晶带。

9. 发明授权

US08133746B2 Method for semiconductor gate hardmask removal and decoupling of implants 有权
标题翻译：半导体门硬掩模移除和植入物去耦方法
公开(公告)号：US08133746B2
公开(公告)日：2012-03-13
申请号：US12714702
申请日：2010-03-01
申请人： Sivananda Kanakasabapathy , Hemanth Jagannathan
发明人： Sivananda Kanakasabapathy , Hemanth Jagannathan
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L29/4908 , H01L29/66772
摘要： A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.
摘要翻译：提供了一种用于制造具有注入的源极/漏极区域和栅极区域的半导体器件的方法，栅极区域在源极/漏极注入期间被栅极硬掩模掩蔽，栅极区域具有层叠在金属层上的金属上的多晶硅栅极高K电介质层。栅极区域和源极/漏极区域可以用膜上的自平面旋转覆盖。该膜可以被覆盖回蚀刻以露出栅极硬掩模，同时保持在植入的源极/漏极区域上的膜上的回蚀刻自平面化旋涂。栅极硬掩模可以被蚀刻回来，同时蚀刻的后膜保持在适当位置以保护植入的源极/漏极区域。栅极区域可以是低能量注入以降低多晶硅层的薄层电阻。然后可以去除蚀刻后的膜。

10. 发明申请

US20110248326A1 STRUCTURE AND METHOD TO INTEGRATE EMBEDDED DRAM WITH FINFET 有权
标题翻译：用FINFET整合嵌入式DRAM的结构和方法
公开(公告)号：US20110248326A1
公开(公告)日：2011-10-13
申请号：US12755487
申请日：2010-04-07
申请人： SIVANANDA KANAKASABAPATHY , Hemanth Jagannathan , Geng Wang
发明人： SIVANANDA KANAKASABAPATHY , Hemanth Jagannathan , Geng Wang
IPC分类号： H01L27/108 , H01L21/28
CPC分类号： H01L27/10826 , H01L21/26586 , H01L21/845 , H01L27/10879 , H01L27/10891 , H01L27/1211
摘要： A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.
摘要翻译：晶体管包括第一鳍结构和形成在衬底上的至少第二鳍结构。在第一和第二翅片结构之间形成深沟槽区域。深沟槽区域延伸穿过衬底的绝缘体层和衬底的半导体层。在深沟槽区域内形成高k金属栅极。在与金属层相邻的深沟槽区域内形成多晶硅层。多晶硅层和高k金属层凹陷在绝缘体层的顶表面下方。深沟槽区域中的多晶带形成在高k金属栅极和多晶硅材料的顶部上。该多晶带的尺寸设计成在第一和第二鳍结构的顶表面下方。第一翅片结构和第二翅片结构电耦合到多晶带。

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