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    • 2. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSOR SYSTEM
    • 半导体集成电路设备和数据处理器系统
    • US20080198148A1
    • 2008-08-21
    • US12020418
    • 2008-01-25
    • Shusaku MIYATAHirofumi Sonoyama
    • Shusaku MIYATAHirofumi Sonoyama
    • G06F3/038
    • G09G3/2096G09G5/39
    • To provide an input interface technique of display data which can contribute to improvement of reliability and high performance of a system in which a semiconductor integrated circuit device including a RAM and a display driver circuit is incorporated. A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
    • 提供可以有助于提高可靠性和高性能的显示数据的输入接口技术,其中并入包括RAM和显示驱动电路的半导体集成电路器件的系统。 半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路,第一高速串行接口电路执行接口 与外部进行控制信息,并且控制电路基于控制信息执行内部操作。 两个高速串行接口电路共享用于存储显示数据信息的RAM。 通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。
    • 5. 发明授权
    • Semiconductor integrated circuit device and data processor system
    • 半导体集成电路器件和数据处理器系统
    • US08018447B2
    • 2011-09-13
    • US12020418
    • 2008-01-25
    • Shusaku MiyataHirofumi Sonoyama
    • Shusaku MiyataHirofumi Sonoyama
    • G09G5/00G09G3/36
    • G09G3/2096G09G5/39
    • To provide an input interface technique of display data which can contribute to improvement of reliability and high performance of a system in which a semiconductor integrated circuit device including a RAM and a display driver circuit is incorporated. A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
    • 提供可以有助于提高可靠性和高性能的显示数据的输入接口技术,其中并入包括RAM和显示驱动电路的半导体集成电路器件的系统。 半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路,第一高速串行接口电路执行接口 与外部进行控制信息,并且控制电路基于控制信息执行内部操作。 两个高速串行接口电路共享用于存储显示数据信息的RAM。 通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。
    • 7. 发明授权
    • Semiconductor integrated circuit device and data processor system
    • 半导体集成电路器件和数据处理器系统
    • US08334860B2
    • 2012-12-18
    • US13223308
    • 2011-08-31
    • Shusaku MiyataHirofumi Sonoyama
    • Shusaku MiyataHirofumi Sonoyama
    • G09G5/00
    • G09G3/2096G09G5/39
    • A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
    • 半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路,第一高速串行接口电路执行接口 与外部进行控制信息,并且控制电路基于控制信息执行内部操作。 两个高速串行接口电路共享用于存储显示数据信息的RAM。 通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。
    • 9. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSOR SYSTEM
    • 半导体集成电路设备和数据处理器系统
    • US20120044218A1
    • 2012-02-23
    • US13223308
    • 2011-08-31
    • SHUSAKU MIYATAHirofumi Sonoyama
    • SHUSAKU MIYATAHirofumi Sonoyama
    • G06F3/038
    • G09G3/2096G09G5/39
    • A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
    • 半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路,第一高速串行接口电路执行接口 与外部进行控制信息,并且控制电路基于控制信息执行内部操作。 两个高速串行接口电路共享用于存储显示数据信息的RAM。 通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。