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1. 发明授权

US06667928B2 Semiconductor device in which a chip is supplied either a first voltage or a second voltage 失效
标题翻译：其中提供芯片的第一电压或第二电压的半导体器件
公开(公告)号：US06667928B2
公开(公告)日：2003-12-23
申请号：US10132248
申请日：2002-04-26
申请人： Kazuki Honma , Yoshiki Kawajiri , Masashi Wada , Mikio Sugawara , Hirofumi Sonoyama
发明人： Kazuki Honma , Yoshiki Kawajiri , Masashi Wada , Mikio Sugawara , Hirofumi Sonoyama
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C5/14 , G11C16/04 , G11C16/30 , G11C29/006 , G11C29/02 , G11C29/12005 , G11C2029/5004
摘要： Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.
摘要翻译：公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量产品和理性需求响应生产管理。半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块，第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

2. 发明申请

US20120044218A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSOR SYSTEM 有权
标题翻译：半导体集成电路设备和数据处理器系统
公开(公告)号：US20120044218A1
公开(公告)日：2012-02-23
申请号：US13223308
申请日：2011-08-31
申请人： SHUSAKU MIYATA , Hirofumi Sonoyama
发明人： SHUSAKU MIYATA , Hirofumi Sonoyama
IPC分类号： G06F3/038
CPC分类号： G09G3/2096 , G09G5/39
摘要： A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
摘要翻译：半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路，第一高速串行接口电路执行接口与外部进行控制信息，并且控制电路基于控制信息执行内部操作。两个高速串行接口电路共享用于存储显示数据信息的RAM。通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。

3. 发明申请

US20080122855A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DISPLAY CONTROLLER 有权
标题翻译：用于显示控制器的半导体集成电路装置
公开(公告)号：US20080122855A1
公开(公告)日：2008-05-29
申请号：US11943366
申请日：2007-11-20
申请人： Hirofumi SONOYAMA , Sosuke Tsuji , Hikaru Shibahara
发明人： Hirofumi SONOYAMA , Sosuke Tsuji , Hikaru Shibahara
IPC分类号： G09G5/39
CPC分类号： G09G5/395 , G09G3/20 , G09G3/3611 , G09G5/363 , G09G5/39 , G09G2310/027 , G09G2310/0278 , G09G2330/08 , G09G2360/123 , G09G2370/08
摘要： The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.
摘要翻译：本文公开的用于显示控制的半导体IC器件旨在实现更高的存储器访问周期，而不增强存储器件的载流能力。 IC器件具有能够存储显示数据的存储单元阵列，能够对显示数据进行写入和读取的外围电路，以及能够控制从存储单元阵列读取和写入操作的控制电路。存储单元阵列包括多个存储块。该控制电路包括控制逻辑，该控制逻辑使得能够以写入操作的并行处理，使得在完成将数据写入存储块之一之前，开始将数据写入另一个存储器块。通过写操作的并行处理来缩短写周期。

4. 发明申请

US20080198148A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND DATA PROCESSOR SYSTEM 有权
标题翻译：半导体集成电路设备和数据处理器系统
公开(公告)号：US20080198148A1
公开(公告)日：2008-08-21
申请号：US12020418
申请日：2008-01-25
申请人： Shusaku MIYATA , Hirofumi Sonoyama
发明人： Shusaku MIYATA , Hirofumi Sonoyama
IPC分类号： G06F3/038
CPC分类号： G09G3/2096 , G09G5/39
摘要： To provide an input interface technique of display data which can contribute to improvement of reliability and high performance of a system in which a semiconductor integrated circuit device including a RAM and a display driver circuit is incorporated. A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
摘要翻译：提供可以有助于提高可靠性和高性能的显示数据的输入接口技术，其中并入包括RAM和显示驱动电路的半导体集成电路器件的系统。半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路，第一高速串行接口电路执行接口与外部进行控制信息，并且控制电路基于控制信息执行内部操作。两个高速串行接口电路共享用于存储显示数据信息的RAM。通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。

5. 发明授权

US08350832B2 Semiconductor integrated circuit device for display controller 有权
标题翻译：用于显示控制器的半导体集成电路器件
公开(公告)号：US08350832B2
公开(公告)日：2013-01-08
申请号：US11943366
申请日：2007-11-20
申请人： Hirofumi Sonoyama , Sosuke Tsuji , Hikaru Shibahara
发明人： Hirofumi Sonoyama , Sosuke Tsuji , Hikaru Shibahara
IPC分类号： G06F3/038 , G06F13/14 , G09G5/00 , G09G5/39 , G06T15/00
CPC分类号： G09G5/395 , G09G3/20 , G09G3/3611 , G09G5/363 , G09G5/39 , G09G2310/027 , G09G2310/0278 , G09G2330/08 , G09G2360/123 , G09G2370/08
摘要： The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.
摘要翻译：本文公开的用于显示控制的半导体IC器件旨在实现更高的存储器访问周期，而不增强存储器件的载流能力。 IC器件具有能够存储显示数据的存储单元阵列，能够对显示数据进行写入和读取的外围电路，以及能够控制从存储单元阵列读取和写入操作的控制电路。存储单元阵列包括多个存储块。该控制电路包括控制逻辑，该控制逻辑使得能够以写入操作的并行处理，使得在完成将数据写入存储块之一之前，开始将数据写入另一个存储器块。通过写操作的并行处理来缩短写周期。

6. 发明授权

US08334860B2 Semiconductor integrated circuit device and data processor system 有权
标题翻译：半导体集成电路器件和数据处理器系统
公开(公告)号：US08334860B2
公开(公告)日：2012-12-18
申请号：US13223308
申请日：2011-08-31
申请人： Shusaku Miyata , Hirofumi Sonoyama
发明人： Shusaku Miyata , Hirofumi Sonoyama
IPC分类号： G09G5/00
CPC分类号： G09G3/2096 , G09G5/39
摘要： A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
摘要翻译：半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路，第一高速串行接口电路执行接口与外部进行控制信息，并且控制电路基于控制信息执行内部操作。两个高速串行接口电路共享用于存储显示数据信息的RAM。通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。

7. 发明授权

US06912172B2 Semiconductor device and method of the semiconductor device 失效
标题翻译：半导体器件的半导体器件和方法
公开(公告)号：US06912172B2
公开(公告)日：2005-06-28
申请号：US10718562
申请日：2003-11-24
申请人： Kazuki Honma , Yoshiki Kawajiri , Masashi Wada , Mikio Sugawara , Hirofumi Sonoyama
发明人： Kazuki Honma , Yoshiki Kawajiri , Masashi Wada , Mikio Sugawara , Hirofumi Sonoyama
IPC分类号： G01R31/28 , G11C5/14 , G11C16/02 , G11C16/16 , G11C16/30 , G11C17/00 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/44 , G11C8/00
CPC分类号： G11C29/028 , G11C5/14 , G11C16/04 , G11C16/30 , G11C29/006 , G11C29/02 , G11C29/12005 , G11C2029/5004
摘要： Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.
摘要翻译：公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量产品和理性需求响应生产管理。半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块，第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

8. 发明授权

US06512398B1 Semiconductor integrated circuit device having reference voltage generating section 失效
标题翻译：具有参考电压产生部分的半导体集成电路器件
公开(公告)号：US06512398B1
公开(公告)日：2003-01-28
申请号：US09572443
申请日：2000-05-17
申请人： Hirofumi Sonoyama , Yoshiki Kawajiri , Masashi Wada , Jun Eto , Shinji Kawai
发明人： Hirofumi Sonoyama , Yoshiki Kawajiri , Masashi Wada , Jun Eto , Shinji Kawai
IPC分类号： G01R1900
CPC分类号： G11C5/143 , G01R19/16552 , G05F3/242 , G11C16/30
摘要： The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.
摘要翻译：通过最小化由于制造过程和/或其他因素导致的电源电压的检测水平的波动，可以显着提高半导体集成电路器件的可靠性。在根据本发明的半导体集成电路器件中，差分放大器电路SA放大表示由参考电压产生部分16产生的参考电压VREF与由电源电压VCC分压所获得的检测电压之间的差异的差分电压，电阻器27和28并将其输出作为检测信号K.参考电压产生部分16从由温度和制造过程影响最小的双极晶体管的基极 - 发射极电压产生参考电压VREF，使得检测的波动电源电压VCC的电平可以最小化。

9. 发明授权

US08018447B2 Semiconductor integrated circuit device and data processor system 有权
标题翻译：半导体集成电路器件和数据处理器系统
公开(公告)号：US08018447B2
公开(公告)日：2011-09-13
申请号：US12020418
申请日：2008-01-25
申请人： Shusaku Miyata , Hirofumi Sonoyama
发明人： Shusaku Miyata , Hirofumi Sonoyama
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/2096 , G09G5/39
摘要： To provide an input interface technique of display data which can contribute to improvement of reliability and high performance of a system in which a semiconductor integrated circuit device including a RAM and a display driver circuit is incorporated. A semiconductor integrated circuit device includes a first high-speed serial interface circuit which has one differential serial data channel and a second high-speed serial interface circuit which has a plurality of differential serial data channels, the first high-speed serial interface circuit performs interface with the outside for control information, and a control circuit performs an internal operation on the basis of the control information. Both of the high-speed serial interface circuits share a RAM for storage of display data information. Whether the data information to be supplied to the RAM is received by using the first high-speed serial interface circuit or the second high-speed serial interface circuit is determined by the control circuit in accordance with the control information that is input to the first high-speed serial interface circuit.
摘要翻译：提供可以有助于提高可靠性和高性能的显示数据的输入接口技术，其中并入包括RAM和显示驱动电路的半导体集成电路器件的系统。半导体集成电路器件包括具有一个差分串行数据通道的第一高速串行接口电路和具有多个差分串行数据通道的第二高速串行接口电路，第一高速串行接口电路执行接口与外部进行控制信息，并且控制电路基于控制信息执行内部操作。两个高速串行接口电路共享用于存储显示数据信息的RAM。通过使用第一高速串行接口电路或第二高速串行接口电路来接收提供给RAM的数据信息是否由控制电路根据输入到第一高速串行接口电路的控制信息来确定 - 串行接口电路。

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