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1. 发明授权

US5432468A Clock generator circuit for use in a personal computer system 失效
标题翻译：用于个人计算机系统的时钟发生器电路
公开(公告)号：US5432468A
公开(公告)日：1995-07-11
申请号：US325153
申请日：1994-10-20
申请人： Shuichi Moriyama , Masayuki Shimura
发明人： Shuichi Moriyama , Masayuki Shimura
IPC分类号： G06F1/06 , G06F1/08 , H03B19/00 , H03K3/01
CPC分类号： G06F1/08
摘要： A frequency dividing circuit/delay circuit is provided to generate a plurality of system clock signals according to the combination of frequency division and the delay based on a fast-speed basic clock signal to determine according to the address signal from a central processing unit (CPU) what the operating cycle of the slave is to select a system clock of optimum frequency or duty ratio for that slave. As a result, it becomes possible to shorten the time required for executing one cycle and, hence, to improve the performance of the whole personal computer system.
摘要翻译：提供了一种分频电路/延迟电路，用于根据基于快速基本时钟信号的分频和延迟的组合产生多个系统时钟信号，以根据来自中央处理单元（CPU）的地址信号来确定）从站的工作周期是为该从站选择最佳频率或占空比的系统时钟。结果，可以缩短执行一个周期所需的时间，从而可以缩短整个个人计算机系统的性能。

2. 发明申请

US20070258292A1 DATA/STROBE ENCODING SCHEME CIRCUIT AND DATA/STROBE ENCODING METHOD 有权
标题翻译：数据/ STROBE编码方案电路和数据/ STROBE编码方法
公开(公告)号：US20070258292A1
公开(公告)日：2007-11-08
申请号：US11696012
申请日：2007-04-03
申请人： Hideki Irisawa , Hiroki Hihara , Shuichi Moriyama
发明人： Hideki Irisawa , Hiroki Hihara , Shuichi Moriyama
IPC分类号： G11C7/10
CPC分类号： H04L7/02 , G11C7/1006 , G11C7/22 , G11C7/222
摘要： In a data/strobe encoding scheme circuit in which data and a strobe signal are transmitted through different lines, changes respectively in the data and the strobe signal are employed as clock signals for a latching operation, and the data is transmitted to a succeeding-stage circuit operating on a second clock signal. The circuit latches predetermined data by an FF circuit and passes a data pair including a signal indicating that the data has been latched and held therein as well as the latched data to the succeeding-stage circuit, activates, if assertion of a signal indicating reception of the data is received from the succeeding-stage circuit, again the FF circuit which has latched the data and has entered a stop state, and receives new data. There is provided a data/strobe encoding scheme circuit and a data/strobe encoding method, it is possible to implement a data/strobe encoding scheme circuit and a data/strobe encoding method capable of realizing a low-cost data/strobe encoding scheme which is independent of LSI device characteristics and which can be easily designed.
摘要翻译：在其中数据和选通信号通过不同的线路发送的数据/选通编码方案电路中，数据和选通信号中的分别改变被用作用于锁存操作的时钟信号，并且数据被发送到后级电路工作在第二个时钟信号上。电路通过FF电路锁存预定数据，并将包括表示数据被锁存和保持在其中的信号以及锁存数据的数据对传送到后级电路，如果断言指示接收到从后级电路再次接收已经锁存数据并已进入停止状态并接收新数据的FF电路。提供数据/选通编码方案电路和数据/选通编码方法，可以实现能够实现低成本数据/选通编码方案的数据/选通编码方案电路和数据/选通编码方法，其中独立于LSI器件特性，可以轻松设计。

3. 发明授权

US08036283B2 Data/strobe encoding scheme circuit and data/strobe encoding method 有权
标题翻译：数据/选通编码方案电路和数据/选通编码方法
公开(公告)号：US08036283B2
公开(公告)日：2011-10-11
申请号：US11696012
申请日：2007-04-03
申请人： Hideki Irisawa , Hiroki Hihara , Shuichi Moriyama
发明人： Hideki Irisawa , Hiroki Hihara , Shuichi Moriyama
IPC分类号： H04B3/00
CPC分类号： H04L7/02 , G11C7/1006 , G11C7/22 , G11C7/222
摘要： In a data/strobe encoding scheme circuit in which data and a strobe signal are transmitted through different lines, changes respectively in the data and the strobe signal are employed as clock signals for a latching operation, and the data is transmitted to a succeeding-stage circuit operating on a second clock signal. The circuit latches predetermined data by an FF circuit and passes a data pair including a signal indicating that the data has been latched and held therein as well as the latched data to the succeeding-stage circuit, activates, if assertion of a signal indicating reception of the data is received from the succeeding-stage circuit, again the FF circuit which has latched the data and has entered a stop state, and receives new data. There is provided a data/strobe encoding scheme circuit and a data/strobe encoding method, it is possible to implement a data/strobe encoding scheme circuit and a data/strobe encoding method capable of realizing a low-cost data/strobe encoding scheme which is independent of LSI device characteristics and which can be easily designed.
摘要翻译：在其中数据和选通信号通过不同的线路发送的数据/选通编码方案电路中，数据和选通信号中的分别改变被用作用于锁存操作的时钟信号，并且数据被发送到后级电路工作在第二个时钟信号上。电路通过FF电路锁存预定数据，并将包括表示数据被锁存和保持在其中的信号以及锁存数据的数据对传送到后级电路，如果断言指示接收到从后级电路再次接收已经锁存数据并已进入停止状态并接收新数据的FF电路。提供数据/选通编码方案电路和数据/选通编码方法，可以实现能够实现低成本数据/选通编码方案的数据/选通编码方案电路和数据/选通编码方法，其中独立于LSI器件特性，可以轻松设计。

4. 发明授权

US06510400B1 Temperature control circuit for central processing unit 有权
标题翻译：中央处理单元温控电路
公开(公告)号：US06510400B1
公开(公告)日：2003-01-21
申请号：US09536149
申请日：2000-03-28
申请人： Shuichi Moriyama
发明人： Shuichi Moriyama
IPC分类号： G06F1500
CPC分类号： G06F1/206
摘要： A CPU temperature control circuit is provided that can vary the clock frequency and the power source voltage of a central processing unit (CPU) while the CPU meets the operational specifications. The comparison circuit 8 compares the temperature of the CPU 1 measured by the CPU temperature sensor 2 with temperature information previously stored in the ROM 6. The CLK and power-source control circuit 9 switches the clock frequency from a high frequency to a low frequency when the temperature of the CPU 1 becomes high. Then, the CKL and power-source control circuit 9 switches the power source voltage from a high voltage to a low voltage at the time the timer 12 counts up. When the temperature of the CPU 1 becomes low, the CLK and power-source control circuit 9 switches the power source voltage from a low voltage to a high voltage. Then, the CLK and power-source control circuit 9 switches the clock frequency from a low frequency to a high frequency at the time the timer 13 counts up.
摘要翻译：提供了CPU温度控制电路，可在CPU满足操作规格的情况下改变中央处理单元（CPU）的时钟频率和电源电压。比较电路8将由CPU温度传感器2测量的CPU 1的温度与先前存储在ROM 6中的温度信息进行比较.C CLK和电源控制电路9将时钟频率从高频切换到低频，当 CPU 1的温度变高。然后，CKL和电源控制电路9在定时器12向上计数时将电源电压从高电压切换到低电压。当CPU 1的温度变低时，CLK和电源控制电路9将电源电压从低电压切换到高电压。然后，CLK和电源控制电路9在定时器13向上计数时将时钟频率从低频切换到高频。

5. 发明授权

US06396321B1 Semiconductor integrated circuit equipped with function for controlling the quantity of processing per unit time length by detecting internally arising delay 有权
标题翻译：半导体集成电路具有通过检测内部产生的延迟来控制每单位时间长度的处理量的功能
公开(公告)号：US06396321B1
公开(公告)日：2002-05-28
申请号：US09511327
申请日：2000-02-23
申请人： Masataka Watanabe , Shuichi Moriyama
发明人： Masataka Watanabe , Shuichi Moriyama
IPC分类号： H03L706
CPC分类号： G06F1/04
摘要： A semiconductor integrated circuit 10 comprises an internal logic circuit 16, a delay detecting circuit 11 which monitors changes in delay length within the semiconductor integrated circuit 10, and a central control circuit 14 which controls the quantity of processing per unit time length by the internal logic circuit 16 on the basis of changes in delay length monitored by the delay detecting circuit 11.
摘要翻译：半导体集成电路10包括内部逻辑电路16，延迟检测电路11，其监视半导体集成电路10内的延迟长度的变化;以及中央控制电路14，其通过内部逻辑控制每单位时间长度的处理量电路16基于由延迟检测电路11监视的延迟长度的变化。

6. 发明授权

US5692150A Cache flash controlling method for cache memory system 失效
标题翻译：缓存闪存控制方法
公开(公告)号：US5692150A
公开(公告)日：1997-11-25
申请号：US508186
申请日：1995-07-27
申请人： Shuichi Moriyama , Kazuhisa Iga
发明人： Shuichi Moriyama , Kazuhisa Iga
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0891
摘要： A cache flash controlling method for a cache memory system of the write back type wherein the time required for discrimination of a dirty line in a flash cycle is reduced and system performances are improved. In the cache controlling method, all lines having tag addresses of a cache memory are divided into a plurality of blocks, and for each of the blocks, a dirty detection bit indicating whether or not a dirty line is present in the block is prepared. For those of the blocks whose data line detection bit indicates presence of no dirty line, lines of the block are invalidated immediately without performing a discrimination operation of a dirty line.
摘要翻译：一种用于回写型高速缓冲存储器系统的高速缓存闪存控制方法，其中在闪速周期中辨别脏线所需的时间减少，系统性能得到改善。在高速缓存控制方法中，将具有高速缓存存储器的标签地址的所有行分成多个块，并且为每个块分配一个指示块中是否存在脏线的脏检测位。对于其数据线检测位指示不存在脏线的块的那些，则块的线将立即无效，而不执行脏线的辨别操作。

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