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    • 1. 发明申请
    • MEMORY INTERFACE CIRCUIT AND TIMING ADJUSTING METHOD
    • 存储器接口电路和时序调整方法
    • US20130070544A1
    • 2013-03-21
    • US13612771
    • 2012-09-12
    • Hitoaki NISHIWAKIShinichiro Ikeda
    • Hitoaki NISHIWAKIShinichiro Ikeda
    • G11C7/00
    • G11C7/00G11C7/1066G11C7/1072G11C11/4076G11C11/4096
    • A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.
    • 一种存储器接口电路,其根据从存储器提供的选通信号来控制从存储器提供的数据的捕获定时,包括控制单元,其控制内部选通门信号的激活定时,其在去激活时屏蔽选通信号, 通过将内部选通栅极信号延迟比时钟信号的一个周期时间短的第一周期,以产生内部选通栅极调整信号,并通过调整调整信号的激活定时。 当选通信号从第一电位变为高于第一电位的第二电位时,或者当选通信号的第一电位持续第二期间或更长时,检测单元输出检测信号。 控制单元根据检测信号调整调整信号的激活定时。