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    • 1. 发明申请
    • VERIFICATION METHOD WITH THE IMPLEMENTATION OF WELL VOLTAGE PSEUDO DIODES
    • 验证方法与实施电压电感二极管
    • US20080189666A1
    • 2008-08-07
    • US11962945
    • 2007-12-21
    • Wen-Hwa M. ChuShaibal BaruaLily X. SpringerJames Homack
    • Wen-Hwa M. ChuShaibal BaruaLily X. SpringerJames Homack
    • G06F17/50
    • G06F17/5081
    • A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.
    • 公开了一种验证电路原理图与相应的集成电路布局之间的一致性的方法。 该方法包括识别与电路原理图的一部分相关联的电压状态,以及将伪二极管分配给与识别的电压条件唯一相关联的电路原理图的部分。 该方法还包括根据所分配的伪二极管的内容对与电路原理图的集成电路布局相关联的伪层进行编码,以及通过从集成电路提取伪层来验证电路原理图和相应的集成电路布局之间的一致性 在电路原理图中布置和比较伪层的信息与所分配的伪二极管。
    • 3. 发明授权
    • Verification method with the implementation of well voltage pseudo diodes
    • 验证方法与实施井电压伪二极管
    • US07895554B2
    • 2011-02-22
    • US11962945
    • 2007-12-21
    • Wen-Hwa M. ChuShaibal BaruaLily X. SpringerJames Homack
    • Wen-Hwa M. ChuShaibal BaruaLily X. SpringerJames Homack
    • G06F9/455
    • G06F17/5081
    • A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.
    • 公开了一种验证电路原理图与相应的集成电路布局之间的一致性的方法。 该方法包括识别与电路原理图的一部分相关联的电压状态,以及将伪二极管分配给与识别的电压条件唯一相关联的电路原理图的部分。 该方法还包括根据所分配的伪二极管的内容对与电路原理图的集成电路布局相关联的伪层进行编码,以及通过从集成电路提取伪层来验证电路原理图和相应的集成电路布局之间的一致性 在电路原理图中布置和比较伪层的信息与所分配的伪二极管。
    • 4. 发明授权
    • Method and apparatus for braking a polyphase DC motor
    • 用于制动多相直流电动机的方法和装置
    • US06177772B1
    • 2001-01-23
    • US09211946
    • 1998-12-15
    • Shaibal BaruaWilliam R. Krenik
    • Shaibal BaruaWilliam R. Krenik
    • H02K710
    • G11B19/20G11B5/54G11B19/22
    • A circuit and method for braking a disk drive when a power fault occurs has a circuit (10) for producing an output signal (28) indicating that the motor of the disk drive has slowed at least to a predetermined rotational speed after the occurrence of the power fault. The components of the circuit (10) may be integrated onto the same integrated circuit as the motor driving circuitry or head retract circuitry. During the time between the occurrence of the power fault and the time the disk drive has slowed to the predetermined rotational speed, the read/write head mechanism (17) is retracted. A braking circuit then brakes the disk drive when the output signal (28) indicates that the motor has slowed, at least to the predetermined rotational speed. The circuit for producing an output signal indicating that the motor has slowed at least to the predetermined rotational speed is actuated by the back-emf (14) generated by the motor failing below a predetermined level.
    • 在发生电源故障时用于制动磁盘驱动器的电路和方法具有用于产生输出信号(28)的电路(10),该电路指示盘驱动器的电动机在发生后至少已经减速到预定的转速 电源故障 电路(10)的组件可以集成到与电动机驱动电路或磁头缩回电路相同的集成电路上。 在电源故障发生与磁盘驱动器已经减速到预定转速的时间之间,读写头机构(17)被缩回。 当输出信号(28)指示电动机已经减速至少达到预定的转速时,制动电路然后制动磁盘驱动器。 用于产生指示电动机至少减速到预定旋转速度的输出信号的电路由电动机产生的反电动势(14)致动低于预定水平。