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1. 发明申请

US20120052690A1 TEMPERATURE ENHANCED ELECTROSTATIC CHUCKING IN PLASMA PROCESSING APPARATUS 失效
标题翻译：等离子体加工装置中的温度增强静电切割
公开(公告)号：US20120052690A1
公开(公告)日：2012-03-01
申请号：US13080561
申请日：2011-04-05
申请人： Sergey G. BELOSTOTSKIY , Michael G. CHAFIN , Jingbao LIU , David PALAGASHVILI
发明人： Sergey G. BELOSTOTSKIY , Michael G. CHAFIN , Jingbao LIU , David PALAGASHVILI
IPC分类号： H01L21/3065 , C23F1/00 , C23F1/08
CPC分类号： H01J37/20 , H01J37/32715 , H01J37/32724 , H01J2237/334 , H01L21/67109 , H01L21/6831
摘要： Methods and systems for temperature enhanced chucking and dechucking of resistive substrates in a plasma processing apparatus are described herein. In certain embodiments, methods and systems incorporate modulating a glass carrier substrate temperature during a plasma etch process to chuck and dechuck the carrier at first temperatures elevated relative to second temperatures utilized during plasma etching. In embodiments, one or more of plasma heat, lamp heat, resistive heat, and fluid heat transfer are controlled to modulate the carrier substrate temperature between chucking temperatures and process temperatures with each run of the plasma etch process.
摘要翻译：本文描述了用于等离子体处理装置中的电阻衬底的温度升高夹持和脱扣的方法和系统。在某些实施方案中，方法和系统包括在等离子体蚀刻工艺期间调节玻璃载体衬底温度，以在相对于在等离子体蚀刻期间使用的第二温度升高的第一温度下卡住和剥离载体。在实施例中，控制等离子体热，灯热，电阻热和流体热传递中的一种或多种，以在等离子体蚀刻工艺的每次运行中调制夹持温度和工艺温度之间的载体衬底温度。

2. 发明申请

US20130105303A1 PROCESS CHAMBER FOR ETCHING LOW K AND OTHER DIELECTRIC FILMS 有权
标题翻译：用于蚀刻低K和其他电介质膜的工艺室
公开(公告)号：US20130105303A1
公开(公告)日：2013-05-02
申请号：US13651074
申请日：2012-10-12
申请人： Dmitry LUBOMIRSKY , Srinivas NEMANI , Ellie YIEH , Sergey G. BELOSTOTSKIY
发明人： Dmitry LUBOMIRSKY , Srinivas NEMANI , Ellie YIEH , Sergey G. BELOSTOTSKIY
IPC分类号： C23F1/00
CPC分类号： H01L21/67069 , C23C16/0245 , H01J37/32091 , H01J37/32357 , H01J37/32477 , H01J37/32532 , H01J37/32587 , H01J37/32715 , H01J2237/3341 , H01L21/02126 , H01L21/3065 , H01L21/3105 , H01L21/31116 , H01L21/31144 , H01L21/67167 , H01L21/67207 , H01L21/6831
摘要： Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.
摘要翻译：描述了用于蚀刻低k和其他电介质膜的方法和处理室。例如，一种方法包括用等离子体处理来修改低k电介质层的部分。选择性地在低k电介质层的掩模层和低k电介质层的未修改部分上蚀刻低k电介质层的改性部分。描述了具有用于交替产生不同等离子体的多个室区的蚀刻室。在实施例中，提供第一电荷耦合等离子体源以在一个操作模式中产生到工件的离子通量，而提供次级等离子体源以在另一个操作模式中提供反应物质通量，而不会对工件产生显着的离子通量。控制器操作以随着时间重复地循环操作模式以去除期望的累积量的电介质材料。

3. 发明申请

US20140375299A1 NON-INTRUSIVE MEASUREMENT OF A WAFER DC SELF-BIAS IN SEMICONDUCTOR PROCESSING EQUIPMENT 有权
标题翻译：半导体加工设备中的直流自偏式非调谐测量
公开(公告)号：US20140375299A1
公开(公告)日：2014-12-25
申请号：US14283159
申请日：2014-05-20
申请人： Sergey G. Belostotskiy , Chinh Dinh , Andrew Nguyen , Michael G. Chafin
发明人： Sergey G. Belostotskiy , Chinh Dinh , Andrew Nguyen , Michael G. Chafin
IPC分类号： G01R19/00 , H01L21/683
CPC分类号： H01J37/00 , H01J37/32715 , H01J37/32935 , H01L21/6833
摘要： A direct (DC) voltage is applied to an electrode at a voltage value to clamp a workpiece to an electrostatic chuck in a processing chamber. The electrode is embedded into the electrostatic chuck. An electrostatic chuck current through the electrode at the DC voltage is measured. A DC self bias induced on the workpiece by a plasma is determined based on the electrostatic chuck current and the applied voltage.
摘要翻译：将直流（DC）电压以电压值施加到电极，以将工件夹紧到处理室中的静电卡盘。电极嵌入静电卡盘。测量在直流电压下通过电极的静电卡盘电流。基于静电卡盘电流和施加的电压来确定通过等离子体在工件上感应的DC自偏压。

4. 发明申请

US20140017898A1 METHOD OF PATTERNING A LOW-K DIELECTRIC FILM 有权
标题翻译：绘制低K电介质膜的方法
公开(公告)号：US20140017898A1
公开(公告)日：2014-01-16
申请号：US13922543
申请日：2013-06-20
申请人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
发明人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
IPC分类号： H01L21/308
CPC分类号： H01L21/308 , H01J37/32357 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a plasma process. The method also involves, in the same operation, removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实例中，图案化低k电介质膜的方法包括在低k电介质层之上形成和图案化掩模层。低k电介质层设置在衬底之上。该方法还涉及用等离子体处理来修饰低k电介质层的暴露部分。该方法在相同的操作中还涉及用远程等离子体处理去除低k电介质层的修改部分对掩模层和低k电介质层的未修改部分选择。

5. 发明申请

US20150380215A1 METHOD OF PATTERNING A LOW-K DIELECTRIC FILM 审中-公开
标题翻译：绘制低K电介质膜的方法
公开(公告)号：US20150380215A1
公开(公告)日：2015-12-31
申请号：US14849296
申请日：2015-09-09
申请人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
发明人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
IPC分类号： H01J37/32
摘要： Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实例中，图案化低k电介质膜的方法包括在低k电介质层之上形成和图案化掩模层，低k电介质层设置在衬底之上。该方法还涉及用无氮等离子体工艺来修饰低k电介质层的暴露部分。该方法还涉及通过远程等离子体处理去除低k电介质层的修改部分对掩模层和低k电介质层的未修改部分有选择性。

6. 发明授权

US09165783B2 Method of patterning a low-k dielectric film 有权
标题翻译：图案化低k电介质膜的方法
公开(公告)号：US09165783B2
公开(公告)日：2015-10-20
申请号：US14059996
申请日：2013-10-22
申请人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
发明人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
IPC分类号： H01L21/302 , H01L21/3105 , H01L21/311 , H01L21/02
CPC分类号： H01J37/3244 , H01J37/32009 , H01L21/02126 , H01L21/3105 , H01L21/31116 , H01L21/31138
摘要： Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实例中，图案化低k电介质膜的方法包括在低k电介质层之上形成和图案化掩模层，低k电介质层设置在衬底之上。该方法还涉及用无氮等离子体工艺来修饰低k电介质层的暴露部分。该方法还涉及通过远程等离子体处理去除低k电介质层的修改部分对掩模层和低k电介质层的未修改部分有选择性。

7. 发明申请

US20140262031A1 MULTI-MODE ETCH CHAMBER SOURCE ASSEMBLY 审中-公开
标题翻译：多模式蚀刻室源组件
公开(公告)号：US20140262031A1
公开(公告)日：2014-09-18
申请号：US13893199
申请日：2013-05-13
申请人： Sergey G. BELOSTOTSKIY , Alexander MARCACCI , Kartik RAMASWAMY , Srinivas D. NEMANI , Andrew NGUYEN , Yogananda SARODE
发明人： Sergey G. BELOSTOTSKIY , Alexander MARCACCI , Kartik RAMASWAMY , Srinivas D. NEMANI , Andrew NGUYEN , Yogananda SARODE
IPC分类号： H01J37/32
CPC分类号： H01J37/3244 , H01J37/32091
摘要： A multi-chambered processing platform includes one or more multi-mode plasma processing systems. In embodiments, a multi-mode plasma processing system includes a multi-mode source assembly having a primary source to drive an RF signal on a showerhead electrode within the process chamber and a secondary source to generate a plasma with by driving an RF signal on an electrode downstream of the process chamber. In embodiments, the primary 7 source utilizes RF energy of a first frequency, while the secondary source utilizes RF energy of second, different frequency. The showerhead electrode is coupled to ground through a frequency dependent filter that adequately discriminates between the first and second frequencies for the showerhead electrode to be RF powered during operation of the primary source, yet adequately grounded during operation of the secondary plasma source without electrical contact switching or reliance on physically moving parts.
摘要翻译：多室处理平台包括一个或多个多模式等离子体处理系统。在实施例中，多模式等离子体处理系统包括多模式源组件，该多模式源组件具有用于驱动处理室内的喷头电极上的RF信号的主要源，以及辅助源以通过在其上驱动RF信号来产生等离子体电极在处理室的下游。在实施例中，主7源使用第一频率的RF能量，而次级源利用第二频率的RF能量。淋浴头电极通过频率相关的滤波器耦合到地面，该滤波器在初级源的操作期间充分地辨别喷头电极的第一和第二频率以进行RF供电，而在没有电接触切换的二级等离子体源的操作期间充分地接地或依赖物理移动部件。

8. 发明申请

US20140120726A1 METHOD OF PATTERNING A LOW-K DIELECTRIC FILM 有权
标题翻译：绘制低K电介质膜的方法
公开(公告)号：US20140120726A1
公开(公告)日：2014-05-01
申请号：US14059996
申请日：2013-10-22
申请人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
发明人： Srinivas D. Nemani , Jeremiah T. Pender , Qingjun Zhou , Dmitry Lubomirsky , Sergey G. Belostotskiy
IPC分类号： H01L21/308 , H01L21/02 , H01L21/3065
CPC分类号： H01J37/3244 , H01J37/32009 , H01L21/02126 , H01L21/3105 , H01L21/31116 , H01L21/31138
摘要： Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实例中，图案化低k电介质膜的方法包括在低k电介质层之上形成和图案化掩模层，低k电介质层设置在衬底之上。该方法还涉及用无氮等离子体工艺来修饰低k电介质层的暴露部分。该方法还涉及通过远程等离子体处理去除低k电介质层的修改部分对掩模层和低k电介质层的未修改部分有选择性。

9. 发明授权

US08580693B2 Temperature enhanced electrostatic chucking in plasma processing apparatus 失效
标题翻译：等离子体处理装置中的温度增强型静电吸盘
公开(公告)号：US08580693B2
公开(公告)日：2013-11-12
申请号：US13080561
申请日：2011-04-05
申请人： Sergey G. Belostotskiy , Michael G. Chafin , Jingbao Liu , David Palagashvili
发明人： Sergey G. Belostotskiy , Michael G. Chafin , Jingbao Liu , David Palagashvili
IPC分类号： H01L21/3065 , C23F1/00
CPC分类号： H01J37/20 , H01J37/32715 , H01J37/32724 , H01J2237/334 , H01L21/67109 , H01L21/6831
摘要： Methods and systems for temperature enhanced chucking and dechucking of resistive substrates in a plasma processing apparatus are described herein. In certain embodiments, methods and systems incorporate modulating a glass carrier substrate temperature during a plasma etch process to chuck and dechuck the carrier at first temperatures elevated relative to second temperatures utilized during plasma etching. In embodiments, one or more of plasma heat, lamp heat, resistive heat, and fluid heat transfer are controlled to modulate the carrier substrate temperature between chucking temperatures and process temperatures with each run of the plasma etch process.
摘要翻译：本文描述了用于等离子体处理装置中的电阻衬底的温度升高夹持和脱扣的方法和系统。在某些实施方案中，方法和系统包括在等离子体蚀刻工艺期间调节玻璃载体衬底温度，以在相对于在等离子体蚀刻期间使用的第二温度升高的第一温度下卡住和剥离载体。在实施例中，控制等离子体热，灯热，电阻热和流体热传递中的一种或多种，以在等离子体蚀刻工艺的每次运行中调制夹持温度和工艺温度之间的载体衬底温度。

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