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1. 发明授权

US09261940B2 Memory system controlling peak current generation for a plurality of memories by monitoring a peak signal to synchronize an internal clock of each memory by a processor clock at different times 有权
标题翻译：存储器系统通过监视峰值信号来控制多个存储器的峰值电流产生，以使每个存储器的内部时钟以不同时间的处理器时钟同步
公开(公告)号：US09261940B2
公开(公告)日：2016-02-16
申请号：US13396618
申请日：2012-02-15
申请人： Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
发明人： Bo-geun Kim , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00 , G06F1/32 , G06F1/14 , G06F13/16 , G06F1/04 , G11C7/22
CPC分类号： G06F1/12 , G06F1/04 , G06F1/14 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F13/1689 , G11C7/222 , Y02D10/14
摘要： A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
摘要翻译：存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与该处理器时钟同步地执行峰值电流产生操作的存储器内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

2. 发明申请

US20110255338A1 Flash memory device and system including the same 有权
标题翻译：闪存设备和系统包括相同
公开(公告)号：US20110255338A1
公开(公告)日：2011-10-20
申请号：US13067746
申请日：2011-06-23
申请人： Jong-Hwa Kim , Young-Joon Choi , Seok-Cheon Kwon
发明人： Jong-Hwa Kim , Young-Joon Choi , Seok-Cheon Kwon
IPC分类号： G11C16/10 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3468 , G11C16/3486 , G11C16/349 , G11C16/3495 , G11C29/00
摘要： The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range.
摘要翻译：本发明提供一种包括闪速存储器件的存储器系统的操作方法。该方法包括对闪速存储器件的所选存储块中包括的至少一个页面进行编程; 以及根据编程页面的循环编号是否超出参考循环范围，确定所选择的存储器块或闪存器件无效。

3. 发明申请

US20090213659A1 FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：闪存存储器件和包括其的闪存存储器系统
公开(公告)号：US20090213659A1
公开(公告)日：2009-08-27
申请号：US12393397
申请日：2009-02-26
申请人： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
发明人： Kyeong-Han Lee , Seok-Cheon Kwon , Dong-Yang Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/26 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C16/08 , G11C16/102 , G11C16/32 , G11C2207/107 , G11C2207/2281
摘要： A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
摘要翻译：一种闪存装置，包括：存储单元阵列; 信号发生器输入第一数据提取信号并输出第二数据获取信号; 以及输出缓冲器电路，被配置为与第二数据提取信号的上升沿和下降沿同步地从存储单元阵列输出数据，其中第二数据取出信号与从输出缓冲器电路输出的数据一起输出。

4. 发明授权

US06282121B1 Flash memory device with program status detection circuitry and the method thereof 有权
标题翻译：具有程序状态检测电路的闪存装置及其方法
公开(公告)号：US06282121B1
公开(公告)日：2001-08-28
申请号：US09656321
申请日：2000-09-06
申请人： Tae-Hee Cho , Seok-Cheon Kwon
发明人： Tae-Hee Cho , Seok-Cheon Kwon
IPC分类号： G11C700
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A nonvolatile semiconductor memory device includes a program state detection circuit for checking a state of programmed memory cells. The program state detection circuit checks program pass/fail using data transmitted through a column selection circuit, according to a column address having redundancy information. Therefore, it is possible to overcome the problem that the memory device is regarded as a fail device owing to a defective column.
摘要翻译：非易失性半导体存储器件包括用于检查编程存储器单元的状态的程序状态检测电路。根据具有冗余信息的列地址，程序状态检测电路使用通过列选择电路发送的数据来检查程序通过/失败。因此，可以克服由于缺陷列而将存储器件视为故障装置的问题。

5. 发明授权

US06236594B1 Flash memory device including circuitry for selecting a memory block 失效
标题翻译：闪存器件包括用于选择存储器块的电路
公开(公告)号：US06236594B1
公开(公告)日：2001-05-22
申请号：US09558665
申请日：2000-04-26
申请人： Seok-Cheon Kwon
发明人： Seok-Cheon Kwon
IPC分类号： G11C1604
CPC分类号： G11C16/08
摘要： A nonvolatile semiconductor memory device has a memory block including a string having a string select transistor responsive to a string select line, a ground select transistor responsive to a ground select line, and a plurality of EEPROM cells responsive to a corresponding plurality of word lines, the plurality of EEPROM cells being serially connected between the string select transistor and the ground select transistor. A first block select transistor is coupled to the ground select transistor. A second block select transistor is coupled to the string select transistor. A plurality of third block select transistors is coupled to the plurality of word lines. A voltage control means provides a first voltage to the first block select transistor and a second voltage to the third block select transistors, the first voltage being less than the second voltage during programming. According to the present invention, a voltage difference occurring between the gate and the drain of the first block select transistor is reduced. The result is a significant stress reduction on the first block select transistor.
摘要翻译：非易失性半导体存储器件具有存储块，该存储块包括响应于串选择线的串选择晶体管的串，响应于接地选择线的地选择晶体管和响应于相应的多个字线的多个EEPROM单元，多个EEPROM单元串联连接在串选择晶体管和接地选择晶体管之间。第一块选择晶体管耦合到接地选择晶体管。第二块选择晶体管耦合到串选择晶体管。多个第三块选择晶体管耦合到多个字线。电压控制装置向第一块选择晶体管提供第一电压，并向第三块选择晶体管提供第二电压，第一电压在编程期间小于第二电压。根据本发明，减小了在第一块选择晶体管的栅极和漏极之间出现的电压差。结果是在第一块选择晶体管上显着降低了应力。

6. 发明授权

US08300467B2 Nonvolatile memory device and related method of operation 有权
标题翻译：非易失存储器件及相关操作方法
公开(公告)号：US08300467B2
公开(公告)日：2012-10-30
申请号：US12821341
申请日：2010-06-23
申请人： Chul Ho Lee , Seok Cheon Kwon
发明人： Chul Ho Lee , Seok Cheon Kwon
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/10
摘要： A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa.
摘要翻译：闪存器件包括交替布置的奇数和偶数存储器单元。奇数和偶数存储单元连接到相应的奇数和偶数位线，连接到相应的奇数和偶数页缓冲器。在闪速存储器件的读取操作中，通过奇数位和偶数位线在两个不同的时间检测数据。在某些实施例中，从奇数页缓冲器读取数据，而数据正通过偶数位线检测，反之亦然。

7. 发明申请

US20120221880A1 MEMORY SYSTEM AND METHOD OF CONTROLLING SAME 有权
标题翻译：记忆系统及其控制方法
公开(公告)号：US20120221880A1
公开(公告)日：2012-08-30
申请号：US13396618
申请日：2012-02-15
申请人： BO-GEUN KIM , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
发明人： BO-GEUN KIM , Kye-hyun Kyung , Jae-yong Jeong , Seung-hun Choi , Seok-cheon Kwon , Chul-ho Lee
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/04 , G06F1/14 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G06F13/1689 , G11C7/222 , Y02D10/14
摘要： A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.
摘要翻译：存储器系统包括产生处理器时钟的控制器和多个存储器件，每个存储器件包括与处理器时钟同步地产生内部时钟的内部时钟发生器，以及与所述处理器时钟同步地执行峰值电流产生操作的存储器内部时钟，其中至少两个存储器件在不同时间产生它们各自的内部时钟，使得相应的峰值电流产生操作在不同的时间执行。

8. 发明申请

US20110090740A1 NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION 有权
标题翻译：非易失性存储器件及其相关操作方法
公开(公告)号：US20110090740A1
公开(公告)日：2011-04-21
申请号：US12821341
申请日：2010-06-23
申请人： Chul Ho LEE , Seok Cheon KWON
发明人： Chul Ho LEE , Seok Cheon KWON
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/10
摘要： A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa.
摘要翻译：闪存器件包括交替布置的奇数和偶数存储器单元。奇数和偶数存储单元连接到相应的奇数和偶数位线，连接到相应的奇数和偶数页缓冲器。在闪速存储器件的读取操作中，通过奇数位和偶数位线在两个不同的时间检测数据。在某些实施例中，从奇数页缓冲器读取数据，而数据正通过偶数位线检测，反之亦然。

9. 发明申请

US20100162164A1 METHOD AND APPARATUS FOR PROVIDING SEARCH SERVICE DURING PROGRAM BROADCASTING 审中-公开
标题翻译：程序广播期间提供搜索服务的方法和装置
公开(公告)号：US20100162164A1
公开(公告)日：2010-06-24
申请号：US12642377
申请日：2009-12-18
申请人： Seok Cheon KWON , Cham Ko , Eun Ju Bae
发明人： Seok Cheon KWON , Cham Ko , Eun Ju Bae
IPC分类号： G06F17/30 , G06F3/048
CPC分类号： H04N7/17318 , G06F16/951 , H04N21/4438 , H04N21/4828
摘要： The invention relates to a method and system for providing a search service to a bidirectional broadcasting terminal during program broadcasting. The invention includes providing a search area for a search service on a screen of the broadcasting terminal in response to key input, providing a first search window to display a representative keyword automatically being as an input with a search word based on an identification of the program, providing a second search window adjacent to the first search window to display a program-related search word automatically being as an input with a completion form of a search word, and providing a third search window adjacent to at least one of the first or second search windows and to display a real-time hot-topic search word automatically being as an input. The second and third search windows to provide an extended pop-up window including a modified word of the search word displayed on the respective search window in response to a selection by a user.
摘要翻译：本发明涉及在节目广播期间向双向广播终端提供搜索服务的方法和系统。本发明包括响应于键输入在广播终端的屏幕上提供用于搜索服务的搜索区域，提供第一搜索窗口，以基于节目的标识自动显示具有搜索词的输入的代表性关键字提供与所述第一搜索窗口相邻的第二搜索窗口，以显示与搜索词的完成形式一起作为输入的程序相关搜索词，以及提供与所述第一或第二搜索窗口中的至少一个相邻的第三搜索窗口搜索窗口并显示一个自动作为输入的实时热门搜索词。所述第二和第三搜索窗口响应于用户的选择而提供包括在相应搜索窗口上显示的搜索词的修改词的扩展弹出窗口。

10. 发明申请

US20100008149A1 FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 有权
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20100008149A1
公开(公告)日：2010-01-14
申请号：US12485983
申请日：2009-06-17
申请人： Jong-Hwa Kim , Seok-Cheon Kwon , Young-Joon Choi
发明人： Jong-Hwa Kim , Seok-Cheon Kwon , Young-Joon Choi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3454 , G11C16/3459
摘要： A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the selected memory cells have been properly programmed.
摘要翻译：一种具有存储单元的闪速存储器件的编程方法，以及执行该方法的闪速存储器件，包括根据加载的数据对所选择的存储器单元进行编程，感测编程的存储器单元的状态，并首先锁定感测的状态，以及确定是否在确定所选择的存储器单元是否被正确地编程之前，参考所加载的数据和锁存状态，已编程所选存储单元中的程序禁止存储单元。

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