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热词
    • 8. 发明授权
    • Command supply device that supplies a command read out from a main memory to a central processing unit
    • 指令供给装置,其将从主存储器读出的命令提供给中央处理单元
    • US07822949B2
    • 2010-10-26
    • US11720011
    • 2005-05-09
    • Satoshi Ogura
    • Satoshi Ogura
    • G06F7/38G06F9/00G06F9/44
    • G06F9/381
    • A command supply device supplies a command sequence that forms a loop. A loop command buffer accumulates a first partial command sequence. The first partial command sequence is a head part of a first command sequence repeatedly supplied to a CPU from among command sequences stored in a main memory, and is accumulated before the first command sequence is supplied to the CPU again. A linking command buffer accumulates a second partial command sequence. The second partial command sequence follows the first partial command sequence in the first command sequence, and is accumulated while the accumulated first partial command sequence in the loop command buffer is supplied to the CPU. A selection circuit supplies, to the CPU, a command from the accumulated second partial command sequence in the linking command buffer when the entirety of the first partial command sequence has been supplied to the CPU.
    • 命令提供设备提供形成循环的命令序列。 循环命令缓冲区累积第一部分命令序列。 第一部分命令序列是从存储在主存储器中的命令序列中重复提供给CPU的第一命令序列的头部,并且在第一命令序列被再次提供给CPU之前累积。 链接命令缓冲区累积第二部分命令序列。 第二部分命令序列遵循第一命令序列中的第一部分命令序列,并且在循环命令缓冲器中累积的第一部分命令序列被提供给CPU时被累加。 当将整个第一部分命令序列提供给CPU时,选择电路向CPU提供来自链接命令缓冲器中的累积的第二部分命令序列的命令。
    • 9. 发明授权
    • Apparatus for pipelining sequential instructions in synchronism with an
operation clock
    • 用于与操作时钟同步地进行顺序指令的装置
    • US6161171A
    • 2000-12-12
    • US105212
    • 1998-06-26
    • Toru MorikawaNobuo HigakiShinji OzakiKeisuke KanekoSatoshi OguraMasato Suzuki
    • Toru MorikawaNobuo HigakiShinji OzakiKeisuke KanekoSatoshi OguraMasato Suzuki
    • G06F9/38G06F12/08G06F13/00
    • G06F9/3867G06F12/0855
    • A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.
    • 需要从数据存储器中读取数据字并将其存储在寄存器组中的特定寄存器中的第一条指令,然后需要分别从寄存器读出的两个操作数和寄存器中的另一个寄存器的第二条指令 设置,应加入管道处理。 在提供具有较高频率的操作时钟的高速模式中,控制指令执行电路和数据存储器之间的数据高速缓冲存储器,以将数据字提供给指令执行的WB(回写)级 电路相对于与第一指令相关联的输入地址在两个周期内。 为了执行第二指令,数据字从WB级提供给指令执行电路的EX(操作执行)级。 在提供具有较低频率的操作时钟的低速模式中,控制数据高速缓冲存储器以相对于输入地址的一个周期内将数据字提供给指令执行电路的MEM(存储器访问)级 与第一条指令相关联。 为了执行第二条指令,将数据字从MEM级旁路到EX级。