会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • Command Supply Device
    • 指令供应装置
    • US20080086621A1
    • 2008-04-10
    • US11720011
    • 2005-05-09
    • Satoshi Ogura
    • Satoshi Ogura
    • G06F13/38
    • G06F9/381
    • A command supply device is provided that efficiently supplies a command sequence that forms a loop. The command supply device includes a loop command buffer in which the command supply device accumulates a first partial command sequence that is a head part of a first command sequence repeatedly supplied to the central processing unit from among command sequences stored in a main memory, before supplying the first command sequence to the central processing unit again. The command supply device also includes a linking command buffer in which the command supply device accumulates a second partial command sequence that follows the first partial command sequence while supplying the first partial command sequence accumulated in the loop command buffer to the central processing unit, when repeatedly supplying the first command sequence to the central processing unit, and a selection circuit which supplies to the central processing unit a command that follows the first partial command sequence from the second partial command sequence accumulated in the linking command buffer, in the case where the entirety of the first partial command sequence has been supplied to the central processing unit.
    • 提供了一种有效提供形成循环的命令序列的命令提供设备。 命令提供装置包括循环命令缓冲器,其中命令提供装置在供应之前从存储在主存储器中的命令序列中累积作为重复提供给中央处理单元的第一命令序列的头部的第一部分命令序列 再次向中央处理单元发送第一个命令序列。 命令提供装置还包括链接命令缓冲器,其中命令提供装置累积在第一部分命令序列之后的第二部分命令序列,同时当重复地向循环命令缓冲器中累积的第一部分命令序列提供给中央处理单元 将第一命令序列提供给中央处理单元;以及选择电路,其在整体的情况下向中央处理单元提供在从连接命令缓冲器中累积的第二部分命令序列之后的第一部分命令序列之后的命令 的第一部分命令序列已经被提供给中央处理单元。
    • 7. 发明授权
    • Pipeline processor capable of reducing branch hazards with small-scale circuit
    • 管道处理器能够通过小规模电路降低分支危险
    • US06189092B1
    • 2001-02-13
    • US09099299
    • 1998-06-18
    • Satoshi OguraShinji Ozaki
    • Satoshi OguraShinji Ozaki
    • G06F938
    • G06F9/381G06F9/322G06F9/325
    • A processor executes a program loop at high speed using a branch target information register instruction which is set immediately before the program loop and a high-speed loop instruction which is set at an end of the program loop. When the branch target information register instruction is decoded by an instruction decoder, code in a fetched instruction buffer is sent to a branch target instruction register, and a shifted pointer in a decoded instruction counter is sent to a branch target fetch address register. After the high-speed loop instruction has been decoded by the instruction decoder and a branch condition is satisfied, the pointer in the branch target fetch address register is sent to a fetched instruction counter and to the decoded instruction counter while the code in the branch target instruction register is sent to a decoded instruction buffer. By using the shifted pointer in the decoded instruction counter, the high-speed loop instruction can be efficiently executed with small-scale hardware.
    • 处理器使用紧接在程序循环之前设置的分支目标信息寄存器指令和设置在程序循环结束的高速循环指令,高速执行程序循环。 当分支目标信息寄存器指令被指令解码器解码时,取出的指令缓冲器中的代码被发送到分支目标指令寄存器,并且解码指令计数器中的移位指针被发送到分支目标提取地址寄存器。 在由指令解码器解码高速循环指令并且分支条件满足之后,转移目标提取地址寄存器中的指针被发送到获取的指令计数器和解码的指令计数器,同时分支目标中的代码 指令寄存器被发送到解码指令缓冲器。 通过使用解码指令计数器中的移位指针,可以用小规模硬件有效地执行高速循环指令。