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1. 发明授权

US06895468B2 Log-structured block system and method 有权
标题翻译：日志结构块系统和方法
公开(公告)号：US06895468B2
公开(公告)日：2005-05-17
申请号：US10060015
申请日：2002-01-29
申请人： Satish L. Rege , Dave Aune
发明人： Satish L. Rege , Dave Aune
IPC分类号： G06F11/14 , G06F11/20 , G06F12/16
CPC分类号： G06F11/2069 , G06F11/1471
摘要： A log-structured block system is provided in which writing log-structured data is done. Subsequently, data mirroring is done. In addition, a data storage system for implementing the log-structured block system is provided.
摘要翻译：提供了一种日志结构的块系统，其中写入日志结构的数据完成。随后，进行数据镜像。另外，提供了一种用于实现日志结构块系统的数据存储系统。

2. 发明授权

US6128717A Method and apparatus for storage application programming interface for digital mass storage and retrieval based upon data object type or size and characteristics of the data storage device 失效
标题翻译：基于数据存储设备的数据对象类型或尺寸和特性的用于数字海量存储和检索的存储应用编程接口的方法和装置
公开(公告)号：US6128717A
公开(公告)日：2000-10-03
申请号：US9622
申请日：1998-01-20
申请人： Joel N. Harrison , Satish L. Rege , Frederick R. Carlson, Jr.
发明人： Joel N. Harrison , Satish L. Rege , Frederick R. Carlson, Jr.
IPC分类号： G06F3/06 , G06F12/08 , G06F12/00
CPC分类号： G06F3/064 , G06F3/0608 , G06F3/061 , G06F3/0676 , G06F12/0862 , G06F12/0866 , G06F2212/6024 , G06F2212/6026
摘要： A storage application programming interface (SAPI) engine is included in a hard disk drive (HDD). The SAPI engine operation is based on intelligent recognition of a plurality of different data objects characterized by type and/or size. The SAPI engine assigns a SAPI descriptor to data objects during its analysis recognition process. The SAPI descriptor identifies the type of the data object, and is used by the HDD to map the data object to a unique logical object address (LOA) space of the HDD tailored to characteristics of the particular disk drive. Using the SAPI descriptor assigned by the SAPI engine enables the HDD to more efficiently store data objects being sent by applications on a host computing system to the disk drive. The efficient storage by the HDD provides a system having improved access performance.
摘要翻译：存储应用程序编程接口（SAPI）引擎包含在硬盘驱动器（HDD）中。 SAPI引擎操作基于以类型和/或尺寸为特征的多个不同数据对象的智能识别。 SAPI引擎在其分析识别过程中为数据对象分配SAPI描述符。 SAPI描述符标识数据对象的类型，并被HDD用于将数据对象映射到适合于特定磁盘驱动器的特性的HDD的唯一逻辑对象地址（LOA）空间。使用SAPI引擎分配的SAPI描述符可使HDD更有效地将由主机计算系统上的应用程序发送的数据对象存储到磁盘驱动器。 HDD的有效存储提供了具有改进的访问性能的系统。

3. 发明授权

US5390299A System for using three different methods to report buffer memory occupancy information regarding fullness-related and/or packet discard-related information 失效
标题翻译：用于使用三种不同方法来报告关于与丰满度和/或丢弃丢弃相关的信息的缓冲存储器占用信息的系统
公开(公告)号：US5390299A
公开(公告)日：1995-02-14
申请号：US814998
申请日：1991-12-27
申请人： Satish L. Rege , Kadangode K. Ramakrishnan , David A. Gagne
发明人： Satish L. Rege , Kadangode K. Ramakrishnan , David A. Gagne
IPC分类号： G06F13/18 , G06F13/38 , G06F13/42 , G06F12/00
CPC分类号： G06F13/387 , G06F13/18
摘要： In a network adapter for a host computer, the data occupancy level of a buffer memory used to store network packets is monitored, and the occupancy level is reported to the host. The buffer memory is organized as a plurality of fixed-size pages. A memory controller uses an allocation counter to track the number of pages available to store incoming data packets, and the value of the allocation counter is compared with a programmable threshold. A data word accompanies each packet delivered to the host to indicate whether the allocation count exceeds the threshold. When the buffer memory has insufficient free space to store an incoming packet, the packet is discarded. The network adapter keeps a count of the number of discarded packets. An adapter manager microprocessor, which is part of the network adapter, reports the count to the host computer on request. The adapter manager also reports the value of the allocation count and other important network adapter variables to the host computer.
摘要翻译：在用于主计算机的网络适配器中，监视用于存储网络分组的缓冲存储器的数据占用级别，并将占用级别报告给主机。缓冲存储器被组织为多个固定大小的页面。存储器控制器使用分配计数器来跟踪可用于存储输入数据分组的页面数量，并将分配计数器的值与可编程阈值进行比较。数据字伴随传送到主机的每个分组，以指示分配计数是否超过阈值。当缓冲存储器没有足够的可用空间来存储传入的数据包时，丢弃数据包。网络适配器保留丢弃数据包的数量。适配器管理器微处理器是网络适配器的一部分，可根据要求向计算机报告计数。适配器管理器还将分配计数和其他重要网络适配器变量的值报告给主机。

4. 发明授权

US4088876A Error correcting circuits and methods for shift register type memories 失效
标题翻译：纠错电路和移位寄存器类型存储器的方法
公开(公告)号：US4088876A
公开(公告)日：1978-05-09
申请号：US751597
申请日：1976-12-17
申请人： Satish L. Rege
发明人： Satish L. Rege
IPC分类号： G06F11/10 , G06F11/14 , G11C29/00
CPC分类号： G06F11/1008 , G06F11/1076 , G06F11/14
摘要： This disclosure relates to error correcting circuits and methods employed thereby for shift register type memories which are formed of a plurality of loops that may be accessed in parallel. Such circuitry is designed to detect when the output of a given loop or shift register becomes a series of ones or a series of zeros which conditions indicate burst mode error. The data bit corresponding to the loop or shift register producing the error is then corrected by complementation.
摘要翻译：本公开涉及由多个可并行访问的移位寄存器型存储器所采用的纠错电路和方法。这种电路被设计为检测给定环路或移位寄存器的输出何时变成一系列的一个或一系列的零，这些条件指示突发模式错误。然后通过互补校正对应于产生错误的循环或移位寄存器的数据位。

5. 发明授权

US5303347A Attribute based multiple data structures in host for network received traffic 失效
标题翻译：主机中基于属性的多个数据结构，用于网络接收流量
公开(公告)号：US5303347A
公开(公告)日：1994-04-12
申请号：US815007
申请日：1991-12-27
申请人： David A. Gagne , Satish L. Rege
发明人： David A. Gagne , Satish L. Rege
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： A method and apparatus for transferring packets of information with different attributes from a device interface to buffers in a host memory dedicated to particular attribute values or ranges of values. The apparatus consists of multiple shared data structures in the form of receive rings, each associated with memory buffers dedicated to a particular range of values for a particular packet attribute. The device interface determines which receive ring is associated with a buffer dedicated to the proper attribute value range by comparing the value of the attribute of the received packet with the values of attributes associated with the buffers of each ring. A sequencing ring is provided to store the order in which each receive ring must be accessed by the host cpu when retrieving packets. This sequencing ring ensures that the host cpu will retrieve the packets in the order in which they were received.
摘要翻译：用于将具有不同属性的信息的分组从设备接口传送到专用于特定属性值或值范围的主机存储器中的缓冲器的方法和装置。该装置由接收环形式的多个共享数据结构组成，每个共享数据结构与专用于特定分组属性的特定范围值的存储器缓冲器相关联。设备接口通过将接收到的分组的属性的值与每个环的缓冲器相关联的属性的值进行比较来确定哪个接收环与专用于适当属性值范围的缓冲器相关联。提供了一个排序环，用于存储在检索数据包时主机cpu中每个接收环必须被访问的顺序。此排序环确保主机cpu将按照接收的顺序检索数据包。

6. 发明授权

US4156287A Fast access charge coupled device memory organizations for a semiconductor chip 失效
公开(公告)号：US4156287A
公开(公告)日：1979-05-22
申请号：US881434
申请日：1978-02-27
申请人： Satish L. Rege , Beng-Yu Woo
发明人： Satish L. Rege , Beng-Yu Woo
IPC分类号： G11C19/28 , G11C21/00
CPC分类号： G11C19/287 , G11C19/285
摘要： This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

7. 发明授权

US4112504A Fast access charge coupled device memory organizations for a semiconductor chip 失效
标题翻译：用于半导体芯片的快速接入电荷耦合器件存储器组织
公开(公告)号：US4112504A
公开(公告)日：1978-09-05
申请号：US734351
申请日：1976-10-20
申请人： Satish L. Rege , Beng-Yu Woo
发明人： Satish L. Rege , Beng-Yu Woo
IPC分类号： G11C19/28 , G11C21/00
CPC分类号： G11C19/287 , G11C19/285
摘要： This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.
摘要翻译：本公开涉及具有并行环路或轨道的快速存取CCD存储器组合，其中可以存储在单个计算器芯片上的数据位的总数取决于由多个刷新放大器组成的开销电路和切换所需的各种开关从存储轨道到读/写位置的存储数据以及刷新放大器的数量以及将时钟脉冲分配到各个存储轨道所需的控制电路。随着开关和刷新放大器的数量增加，存储位所需的总面积也增加。随着时钟开关的数量增加，半导体芯片的功耗降低。随着刷新放大器的数量增加，访问时间和总服务时间减少。公开了许多不同的最佳记忆组织。

8. 发明授权

US5612897A Symmetrically switched multimedia system 失效
标题翻译：对称切换多媒体系统
公开(公告)号：US5612897A
公开(公告)日：1997-03-18
申请号：US620110
申请日：1996-03-21
申请人： Satish L. Rege
发明人： Satish L. Rege
IPC分类号： G06F11/20 , H04L12/56 , H04L29/06 , H04L12/00
CPC分类号： H04L49/254 , H04L29/06 , H04L49/252 , H04L65/4076 , H04L65/4084 , G06F2211/1028 , H04L29/06027 , H04L49/3027 , H04L67/42
摘要： A multimedia system for delivering multimedia content items to customer premises equipment via a circuit of a communications network includes a plurality of substantially identical nodes connected in a symmetric mesh. Each node includes a switch and a server. The server includes disk storage for the multimedia content, a switch interface for connecting the server to the switch, and a network adapter for connecting the server to the communications network. Source nodes fetch data from disk, routing nodes transport data among nodes, and destination nodes transport the data to the communications network. The switch is a store-and-forward switch including direct memory access engine for pulling data into the switch, and a buffer for storing data to be forwarded to another switch. Portions of each content item are distributed substantially equally over the available storage media to improve load balancing and data redundancy.
摘要翻译：用于经由通信网络的电路将多媒体内容项目提供给客户驻地设备的多媒体系统包括以对称网格连接的多个基本相同的节点。每个节点包括交换机和服务器。服务器包括用于多媒体内容的磁盘存储器，用于将服务器连接到交换机的交换机接口以及用于将服务器连接到通信网络的网络适配器。源节点从磁盘获取数据，路由节点在节点之间传输数据，目的节点将数据传输到通信网络。交换机是存储转发交换机，包括用于将数据拉入交换机的直接存储器访问引擎，以及用于存储要转发到另一交换机的数据的缓冲器。每个内容项的部分基本上均等地分布在可用的存储介质上以改善负载平衡和数据冗余。

9. 发明授权

US5440690A Network adapter for interrupting host computer system in the event the host device driver is in both transmit and receive sleep states 失效
标题翻译：在主机设备驱动程序处于发送和接收睡眠状态的情况下，用于中断主机系统的网络适配器
公开(公告)号：US5440690A
公开(公告)日：1995-08-08
申请号：US225367
申请日：1994-04-08
申请人： Satish L. Rege , Andrew P. Russo
发明人： Satish L. Rege , Andrew P. Russo
IPC分类号： G06F5/10 , G06F13/12 , G06F13/24 , G06F13/00
CPC分类号： G06F5/10 , G06F13/128 , G06F13/24 , G06F2205/108
摘要： A network adapter with an interrupt generation circuit to minimize the number of host computer system interrupts needed to notify the host computer system that the network adapter has consumed one or more host memory buffers. The interrupt generation circuit issues an interrupt to the host computer system when the host computer system has entered both a transmit sleep state and a receive sleep state, and the network adapter has consumed a host memory buffer not processed by the host computer system. When the host computer system has no work to do with respect to transmit buffers in the host computer memory, it enters a transmit sleep state and indicates to the network adapter the last transmit buffer it processed. When the host computer system has no work to do with respect to receive buffers in the host computer memory, it enters a receive sleep state and indicates to the network adapter the last receive buffer it processed. If subsequent to both these indications, the network adapter consumes a host memory buffer that the host computer system has not processed, the interrupt generation circuit issues an interrupt to the host computer system. The network adapter further includes means for the host computer system to notify the network adapter that the host computer has produced multiple host memory buffers for the network adapter to consume.
摘要翻译：具有中断产生电路的网络适配器，以最小化通知主机系统网络适配器已消耗一个或多个主机内存缓冲区所需的主机计算机系统中断次数。当主计算机系统进入发送休眠状态和接收休眠状态时，中断产生电路向主计算机系统发出中断，并且网络适配器已经消耗了未被主机系统处理的主机存储器缓冲器。当主计算机系统对于主计算机存储器中的发送缓冲器没有任何工作时，它进入发送休眠状态，并向网络适配器指示其处理的最后发送缓冲器。当主计算机系统与主计算机存储器中的接收缓冲区无关的工作时，它进入接收休眠状态，并向网络适配器指示其处理的最后一个接收缓冲器。如果在这两个指示之后，网络适配器消耗主机系统尚未处理的主机内存缓冲区，则中断产生电路向主机系统发出中断。网络适配器还包括用于主计算机系统通知网络适配器主机计算机已经产生用于网络适配器消耗的多个主机存储器缓冲器的装置。

10. 发明授权

US4321694A Charge coupled device memory with enhanced access features 失效
标题翻译：电荷耦合器件存储器具有增强的访问功能
公开(公告)号：US4321694A
公开(公告)日：1982-03-23
申请号：US74831
申请日：1979-09-12
申请人： Godavarish Panigrahi , Satish L. Rege
发明人： Godavarish Panigrahi , Satish L. Rege
IPC分类号： G11C19/38 , G11C21/00
CPC分类号： G11C19/38 , G11C21/00
摘要： A circulating shift register memory, particularly adaptable to charge coupled device technology, wherein a plurality of circulating shift registers are arranged to provide a matrix of data bits accessible at a common data front. Address counter circuitry cooperating with the register clocking circuits selects a particular bit location on the data front for each shift of the shift registers. Depending upon a mode signal and beginning address from a host system, the address counter circuitry provides successive accesses in predetermined patterns, for example along a row, column or diagonal of the bit matrix.
摘要翻译：循环移位寄存器存储器，特别适用于电荷耦合器件技术，其中多个循环移位寄存器被布置成提供在公共数据前端可访问的数据位矩阵。与寄存器时钟电路配合的地址计数器电路为移位寄存器的每个移位选择数据正面上的特定位位置。取决于来自主机系统的模式信号和开始地址，地址计数器电路以预定模式提供连续访问，例如沿着位矩阵的行，列或对角线。

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