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1. 发明授权

US4321694A Charge coupled device memory with enhanced access features 失效
标题翻译：电荷耦合器件存储器具有增强的访问功能
公开(公告)号：US4321694A
公开(公告)日：1982-03-23
申请号：US74831
申请日：1979-09-12
申请人： Godavarish Panigrahi , Satish L. Rege
发明人： Godavarish Panigrahi , Satish L. Rege
IPC分类号： G11C19/38 , G11C21/00
CPC分类号： G11C19/38 , G11C21/00
摘要： A circulating shift register memory, particularly adaptable to charge coupled device technology, wherein a plurality of circulating shift registers are arranged to provide a matrix of data bits accessible at a common data front. Address counter circuitry cooperating with the register clocking circuits selects a particular bit location on the data front for each shift of the shift registers. Depending upon a mode signal and beginning address from a host system, the address counter circuitry provides successive accesses in predetermined patterns, for example along a row, column or diagonal of the bit matrix.
摘要翻译：循环移位寄存器存储器，特别适用于电荷耦合器件技术，其中多个循环移位寄存器被布置成提供在公共数据前端可访问的数据位矩阵。与寄存器时钟电路配合的地址计数器电路为移位寄存器的每个移位选择数据正面上的特定位位置。取决于来自主机系统的模式信号和开始地址，地址计数器电路以预定模式提供连续访问，例如沿着位矩阵的行，列或对角线。

2. 发明授权

US3975717A Charge coupled device stack memory organization and refresh method 失效
标题翻译：电荷耦合器件堆栈存储器组织和刷新方法
公开(公告)号：US3975717A
公开(公告)日：1976-08-17
申请号：US504067
申请日：1974-09-09
申请人： Godavarish Panigrahi
发明人： Godavarish Panigrahi
IPC分类号： G11C11/56 , G06F5/08 , G06F7/78 , G11C19/28 , G11C27/04 , G11C11/40
CPC分类号： G06F7/78 , G06F5/08 , G11C19/287
摘要： An extendable memory organization capable of last-in-first-out or first-in-first-out operation comprising a stack of charge coupled device shift registers arranged such that each register shifts data in a direction opposite to that of its adjoining neighbors in the stack. Gating interconnecting the registers is selectively operable to enable read and write operations at either of the stack and up or down shifting of data in the stack. In particular, the gating and control structure permits refreshing the memory by alternately shifting each stored data word up and down between two storage positions in the stack. In one embodiment, gating and control is implemented in a sandwich structure incorporated into the charge coupled shift register channel.
摘要翻译：一种能够进行先进先出或先进先出操作的可扩展存储器组合，其包括一堆电荷耦合器件移位寄存器，其被布置成使得每个寄存器在与其相邻邻居的方向相反的方向上移位数据堆栈互连寄存器的门控可选择性地可操作以使得堆栈中的任何一个读取和写入操作以及堆栈中的数据的上下移位。特别地，选通和控制结构允许通过在堆叠中的两个存储位置之间交替地移位每个存储的数据字来刷新存储器。在一个实施例中，门控和控制在并入电荷耦合移位寄存器通道的夹层结构中实现。

3. 发明授权

US4065756A Associative memory with neighboring recirculated paths offset by one bit 失效
标题翻译：与相邻再循环路径的关联存储器偏移一位
公开(公告)号：US4065756A
公开(公告)日：1977-12-27
申请号：US666575
申请日：1976-03-15
申请人： Godavarish Panigrahi
发明人： Godavarish Panigrahi
IPC分类号： G06F17/30 , G11C19/28 , G11C15/04 , G11C21/00
CPC分类号： G06F17/30982 , G11C19/287
摘要： This disclosure relates to a charge coupled device memory that is content or associative addressable with the respective word locations (loops) being searched concurrently although word access is serial in manner. Data bits in respective word loops are arranged in a staggered manner such that when the first bit of the first word is at its comparison location, the second bit of the second word is at its comparison location and so forth. The comparand and mask bits are shifted serially from comparison location to comparison location and recirculated in synchronism with the recirculation of the word loops. Content addressing logic includes a series of match bit shift registers, one for each comparison location, to record match occurrences. When a word match occurs, the address of the respective word loop is sent to the memory to read out the data bits stored therein. Various embodiments are disclosed to illustrate that the memory may be formed of any number of word locations having any number of bit positions per word.
摘要翻译：本公开涉及一种电荷耦合器件存储器，其可以同时被搜索的各个字位置（循环）进行内容或关联地寻址，尽管字访问是串行的。各个字循环中的数据位以交错方式布置，使得当第一个字的第一位在其比较位置时，第二个字的第二位在其比较位置等等。比较和掩码位从比较位置到比较位置串行移位，并与字循环的再循环同步再循环。内容寻址逻辑包括一系列匹配位移位寄存器，每个比较位置一个用于记录匹配事件。当发生字匹配时，相应字循环的地址被发送到存储器以读出存储在其中的数据位。公开了各种实施例，以说明存储器可以由具有每个字的任何位数位置的任意数量的字位置形成。

4. 发明授权

US4084154A Charge coupled device memory system with burst mode 失效
标题翻译：带触发模式的充电耦合器件存储器系统
公开(公告)号：US4084154A
公开(公告)日：1978-04-11
申请号：US573805
申请日：1975-05-01
申请人： Godavarish Panigrahi
发明人： Godavarish Panigrahi
IPC分类号： G11C19/28 , G11C7/00
CPC分类号： G11C19/282 , G11C19/287
摘要： A circular shift register memory system comprising L sections each having K circular charge storage shift registers of N bits each for storing blocks of N, K-bit words and accessing the words or blocks thereof in parallel. The L memory sections are refreshed by N-bit clock bursts which are successively and periodically applied to the memory sections by a refresh counter, decoder and gating logic. A read/write decoder decodes memory section addresses and controls the application of N-bit clock bursts to the particular addressed memory sections for access purposes. In a random access mode, word access is facilitated by counters which count the number of read/write or refresh clock pulses for comparison to a word address. A memory section comparator prevents interference between access and refresh operations by inhibiting the refresh circuitry if the refresh counter directs refresh of a memory section undergoing access and by inhibiting the read/write circuitry in certain cases where access is requested to a memory section undergoing refresh.

5. 发明授权

US4011548A Three phase charge-coupled device memory with inhibit lines 失效
标题翻译：三相电荷耦合器件存储器，禁止线
公开(公告)号：US4011548A
公开(公告)日：1977-03-08
申请号：US592401
申请日：1975-07-02
申请人： Godavarish Panigrahi
发明人： Godavarish Panigrahi
IPC分类号： G11C19/28 , H01L27/105 , G11C11/44
CPC分类号： H01L27/1057 , G11C19/287
摘要： A charge coupled device shift register memory structure wherein the shift registers may be selectively activated. Each shift register is clocked by a common set of clock phase electrodes. Individual inhibit lines are placed over each shift register channel, and by applying appropriate voltages to these inhibit lines shifting of data in the underlying channel is prevented. In one embodiment, a channel decoder, common source and drain lines and cooperating gating circuitry facilitate read/write and refresh operations.
摘要翻译：电荷耦合器件移位寄存器存储器结构，其中移位寄存器可被选择性地激活。每个移位寄存器由一组共同的时钟相位电极计时。各个禁止线置于每个移位寄存器通道上，并且通过对这些禁止线施加适当的电压来防止下面通道中的数据移位。在一个实施例中，信道解码器，公共源极线和漏极线以及协同选通电路便于读/写和刷新操作。

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