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1. 发明申请

US20060166429A1 Vertical replacement-gate junction field-effect transistor 审中-公开
公开(公告)号：US20060166429A1
公开(公告)日：2006-07-27
申请号：US11390015
申请日：2006-03-27
申请人： Samir Chaudhry , Paul Layman , John McMacken , Ross Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , Ross Thomson , Jack Zhao
IPC分类号： H01L21/8238 , H01L21/337 , H01L21/336
CPC分类号： H01L29/66909 , H01L21/823487 , H01L27/088 , H01L27/098 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/78642 , H01L29/8083
摘要： An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

2. 发明申请

US20050048709A1 Multiple operating voltage vertical replacement-gate (VRG) transistor 有权
标题翻译：多工作电压垂直置换栅（VRG）晶体管
公开(公告)号：US20050048709A1
公开(公告)日：2005-03-03
申请号：US10684713
申请日：2003-10-14
申请人： Paul Layman , John McMacken , J. Thomson , Samir Chaudhry , Jack Zhao
发明人： Paul Layman , John McMacken , J. Thomson , Samir Chaudhry , Jack Zhao
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/088 , H01L27/092 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/823437 , H01L21/823487 , H01L29/7827 , Y10S438/981
摘要： An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions. In an associated method of manufacturing the semiconductor device, a first and second source/drain regions are formed in a semiconductor layer. A first field-effect transistor gate region, including a channel and a gate electrode is formed over the first source drain region and a second field-effect transistor gate region is formed over the second source/drain region. Fifth and sixth source/drain regions are then formed for each of the first and second field-effect transistors and further having the appropriate conductivity type. Variable thickness gate oxides are created by appropriately masking, etching, and regrowing gate oxides. As a result, the formed transistors operate at different operating voltages. Thus a plurality of such transistors operating at different operating voltage (as a function of the gate oxide thickness) can be formed in an integrated circuit.
摘要翻译：用于创建多个工作电压MOSFET的架构。通常，集成电路结构包括具有沿着平面形成的主表面的半导体区域和形成在表面中的第一和第二间隔开的掺杂区域。形成与第一区域不同的导电类型的沟道的第三掺杂区域位于第一区域上方。具有不同导电性并形成沟道的第四掺杂区位于第二区上方。为两个晶体管中的每个晶体管产生栅极结构的过程允许在两个晶体管之间形成不同厚度的氧化物层。因此，晶体管能够在不同的工作电压（包括不同的阈值电压）下工作。每个晶体管还包括分别位于第三和第四区域上的第五和第六层，并且相对于第三和第四区域具有相反的导电类型。在制造半导体器件的相关方法中，在半导体层中形成第一和第二源/漏区。在第一源极漏极区域上形成包括沟道和栅电极的第一场效应晶体管栅极区域，并且在第二源极/漏极区域上形成第二场效应晶体管栅极区域。然后为第一和第二场效应晶体管中的每一个形成第五和第六源极/漏极区域，并且还具有适当的导电类型。通过适当地掩蔽，蚀刻和再生栅极氧化物来产生可变厚度的栅极氧化物。结果，形成的晶体管在不同的工作电压下工作。因此，可以在集成电路中形成以不同工作电压（与栅极氧化物厚度的函数））工作的多个这样的晶体管。

3. 发明申请

US20070238243A1 Fabrication method 有权
标题翻译：制作方法
公开(公告)号：US20070238243A1
公开(公告)日：2007-10-11
申请号：US11809873
申请日：2007-06-01
申请人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
IPC分类号： H01L21/765
CPC分类号： H01L29/66666 , H01L27/0629 , H01L27/10808 , H01L27/10852 , H01L27/10861 , H01L27/10873 , H01L27/10876 , H01L28/60 , H01L29/66181 , H01L29/945
摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.
摘要翻译：与集成电路中使用的垂直MOSFET器件和电容器相关的工艺和架构。通常，集成电路结构包括具有沿其平面形成的主表面的半导体层，并且还包括形成在表面中的第一掺杂区域。与第一掺杂区域不同的导电类型的第二掺杂区域位于第一区域上方。与第二区域不同的导电类型的第三掺杂区域位于第二区域上方。在本发明的一个实施例中，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。集成电路还包括具有底板，电介质层和顶部电容器板的电容器。在相关联的制造方法中，在半导体层上形成从由场效应晶体管的源极区域和漏极区域中选择的第一器件区域。第一场效应晶体管栅极区域形成在第一器件区域上。在半导体层上还形成有包括设置在其间的介电层的顶层和底层的电容器。在另一个实施例中，电容器层形成在形成在半导体层中的沟槽或窗口内。

4. 发明申请

US20070111414A1 A Vertical Replacement-Gate Silicon-On-Insulator Transistor 有权
标题翻译：垂直替代栅极硅绝缘体晶体管
公开(公告)号：US20070111414A1
公开(公告)日：2007-05-17
申请号：US11419356
申请日：2006-05-19
申请人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
IPC分类号： H01L21/337
CPC分类号： H01L29/42392 , H01L21/84 , H01L27/1203 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a relatively thin vertical layer of single crystalline material. A MOSFET gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel, the regions being appropriately doped to effect MOSFET action.
摘要翻译：一种用于创建垂直绝缘体上硅的MOSFET的架构。通常，集成电路结构包括具有沿着平面形成的主表面的半导体区域和形成在表面中的第一源极/漏极接触区域。相对薄的单晶层在主表面上垂直取向，并且包括第一源极/漏极掺杂区域，在该第一源极/漏极掺杂区域上定位有掺杂沟道区，其上定位有第二源极/漏极区。邻近所述第一和第二源极/漏极区域和所述沟道区域设置绝缘层，用作SOI器件的绝缘材料。在另一个实施例中，绝缘材料仅与所述第一和所述第二源极/漏极区相邻。导电区域与通道区域相邻，用于将沟道区域的背面连接到地，例如以防止沟道区域浮动。在制造半导体器件的相关方法中，第一源极/漏极区形成在相对薄的单晶材料垂直层中。在第一源极/漏极区域上形成包括沟道和栅电极的MOSFET栅极区域。然后在该通道上形成第二源极/漏极区域，该区域被适当地掺杂以实现MOSFET的动作。

5. 发明申请

US20070228440A1 Structure and fabrication method for capacitors integratible with vertical replacement gate transistors 失效
公开(公告)号：US20070228440A1
公开(公告)日：2007-10-04
申请号：US11809686
申请日：2007-05-31
申请人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
IPC分类号： H01L29/94
CPC分类号： H01L29/66666 , H01L27/0629 , H01L27/10808 , H01L27/10852 , H01L27/10861 , H01L27/10873 , H01L27/10876 , H01L28/60 , H01L29/66181 , H01L29/945
摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.

6. 发明申请

US20060166395A1 High-density inter-die interconnect structure 审中-公开
公开(公告)号：US20060166395A1
公开(公告)日：2006-07-27
申请号：US11392375
申请日：2006-03-29
申请人： Paul Layman , John McMacken
发明人： Paul Layman , John McMacken
IPC分类号： H01L21/00
CPC分类号： H01L27/1465 , H01L24/81 , H01L27/14618 , H01L27/14621 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L27/1469 , H01L2224/16145 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01037 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/0106 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/12036 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated circuit fabricated structure provide electrical connection between individual photo sensors and the operative circuitry on the second integrated circuit fabricated structure.

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