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1. 发明授权

US08868962B2 Monitoring circuit and method 有权
标题翻译：监控电路及方法
公开(公告)号：US08868962B2
公开(公告)日：2014-10-21
申请号：US13368383
申请日：2012-02-08
申请人： James Edward Myers , David Walter Flynn , Bal S Sandhu
发明人： James Edward Myers , David Walter Flynn , Bal S Sandhu
IPC分类号： G06F1/04 , G01K7/00
CPC分类号： G01K7/346
摘要： A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.
摘要翻译：集成电路的监视电路包括非温度反相电路和温度反相电路。测量两个电路的工作参数，表示各个电路中信号的传播速度。响应于温度变化，非温度反相电路减慢，温度反转电路加速。相比之下，响应于工作电压的变化，两个电路都加速或减慢。响应于温度的这种分歧和对电压的类似响应使得监测电路能够区分工作电压的变化和工作温度的变化。

2. 发明授权

US08427245B2 Ultra low power oscillator 有权
标题翻译：超低功耗振荡器
公开(公告)号：US08427245B2
公开(公告)日：2013-04-23
申请号：US13067471
申请日：2011-06-02
申请人： Bal S Sandhu
发明人： Bal S Sandhu
IPC分类号： H03B5/24
CPC分类号： H03K3/0315 , H03K3/012
摘要： A frequency generator is provided which is embodied in an integrated circuit manufactured at a process node below 100 nm. The frequency generator comprises a current starved oscillator configured to generate an output frequency signal in dependence on a voltage of a bias signal and a self-biased current generator configured to generate the bias signal, wherein the self-biased current generator comprises a first transistor and a second transistor connected in series. The bias signal is taken from a midpoint between the first transistor and the second transistor, and respective gates of the first and second transistors are connected to keep said first and second transistors in a cut-off state. Accordingly the self-biased current generator operates in a deep sub-threshold state and a current of said bias signal is dependent on a leakage current in the first and second transistors.
摘要翻译：提供一种频率发生器，其实现在在100nm以下的处理节点处制造的集成电路。所述频率发生器包括：当前饥饿振荡器，其被配置为根据偏置信号的电压产生输出频率信号，以及配置成产生所述偏置信号的自偏置电流发生器，其中所述自偏置电流发生器包括第一晶体管和串联连接的第二晶体管。偏置信号取自第一晶体管和第二晶体管之间的中点，并且连接第一和第二晶体管的各个栅极以将所述第一和第二晶体管保持在截止状态。因此，自偏置电流发生器工作在深亚阈值状态，并且所述偏置信号的电流取决于第一和第二晶体管中的漏电流。

3. 发明授权

US08395440B2 Apparatus and method for controlling power gating in an integrated circuit 有权
标题翻译：用于控制集成电路中的电源门控的装置和方法
公开(公告)号：US08395440B2
公开(公告)日：2013-03-12
申请号：US12926531
申请日：2010-11-23
申请人： Bal S. Sandhu , Satchin Satish Idgunji , David Walter Flynn
发明人： Bal S. Sandhu , Satchin Satish Idgunji , David Walter Flynn
IPC分类号： G05F1/10
CPC分类号： H03K19/0008 , H03K17/145 , H03K19/00369 , H03K2017/066
摘要： An integrated circuit comprises a block of components to be power gated and power gating circuitry for selectively isolating the components from the source voltage supply to achieve such power gating. A voltage regulator provides a control voltage to the power gating circuitry when performing power gating operations. The control voltage may be set to any of a plurality of predetermined voltage levels. An adaptive controller receives operating parameter data from either or both of the block of components and the power gating circuitry, that operating parameter data being indicative of leakage current. The adaptive controller issues a feedback signal to the voltage regulator whose value depends on the received operating parameter data. The voltage regulator responds to the feedback signal to change the control voltage between the predetermined voltage levels until the operating parameter data indicates that a desired leakage current is obtained within the power gating circuitry.
摘要翻译：集成电路包括要被电源门控的组件块和用于选择性地将组件与源电压源隔离以实现这种电源门控的电源门控电路。当执行电源门控操作时，电压调节器为电源门控电路提供控制电压。控制电压可以被设置为多个预定电压电平中的任何一个。自适应控制器从组件块和功率选通电路中的一个或两个接收操作参数数据，该操作参数数据表示泄漏电流。自适应控制器向电压调节器发出反馈信号，该值取决于接收到的操作参数数据。电压调节器响应于反馈信号以改变在预定电压电平之间的控制电压，直到操作参数数据指示在功率选通电路内获得期望的泄漏电流。

4. 发明授权

US6140860A Thermal sensing circuit 有权
标题翻译：热敏电路
公开(公告)号：US6140860A
公开(公告)日：2000-10-31
申请号：US149698
申请日：1998-09-08
申请人： Bal S. Sandhu , Dennis Reinhardt
发明人： Bal S. Sandhu , Dennis Reinhardt
IPC分类号： G05F3/24 , G06F1/20 , H03F3/45 , H03F3/72 , H03K5/24 , H03K17/14 , H01L35/00
CPC分类号： G06F1/324 , G05F3/245 , G06F1/20 , H03F3/45479 , H03F3/72 , H03K5/2481 , Y02B60/1217
摘要： An apparatus for use with a semiconductor substrate includes a digital interface, a digital-to-analog converter and a thermal sensor circuit. The digital interface stores a value that indicates a desired thermal threshold, and the digital-to-analog converter provides an analog signal that indicates the value. The thermal sensor circuit uses the analog signal to set the desired thermal threshold and indicate when a temperature of the substrate exceeds the thermal threshold.
摘要翻译：一种与半导体衬底一起使用的装置包括数字接口，数模转换器和热传感器电路。数字接口存储指示所需热阈值的值，并且数模转换器提供指示该值的模拟信号。热传感器电路使用模拟信号来设置所需的热阈值，并指示衬底的温度何时超过热阈值。

5. 发明授权

US5521874A High speed differential to single ended sense amplifier 失效
标题翻译：高速差分至单端读出放大器
公开(公告)号：US5521874A
公开(公告)日：1996-05-28
申请号：US357859
申请日：1994-12-14
申请人： Bal S. Sandhu
发明人： Bal S. Sandhu
IPC分类号： G11C7/06 , G11C7/02
CPC分类号： G11C7/062
摘要： A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.
摘要翻译：差分至单端读出放大器利用最小级数将从互补位线接收的差分输入信号转换成指示存储在连接到互补位线的选定存储单元中的数据的状态的单端输出信号。该电路被构造为以低电压摆幅工作，从而增加开关速度，从而增加感测速度。读出放大器包括断电功能以及在处于待机操作模式期间对其输出端子进行三态的能力，在该待机操作模式下，它能够读取输入信号的逻辑电平。在一个实施例中，当输出级三态时，使用简单寄存器来锁存输出信号，以在执行后续检测操作时继续提供有效的输出信号。

6. 发明申请

US20140035661A1 AN INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING LOAD ON THE OUTPUT FROM ON-CHIP VOLTAGE GENERATION CIRCUITRY 有权
标题翻译：用于控制来自片上电压发生电路的输出上的负载的集成电路和方法
公开(公告)号：US20140035661A1
公开(公告)日：2014-02-06
申请号：US13562516
申请日：2012-07-31
申请人： James Edward MYERS , Parameshwarappa Anand Kumar SAVANTH , David Walter FLYNN , David William HOWARD , Bal S. SANDHU
发明人： James Edward MYERS , Parameshwarappa Anand Kumar SAVANTH , David Walter FLYNN , David William HOWARD , Bal S. SANDHU
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry. This provides a particularly simple and effective mechanism for providing an additional load on the output node which can be altered with the aim of offsetting variation in the load on the output node presented by the circuit block, thus allowing the variation in the voltage output from the on-chip voltage generation circuitry to be controlled.
摘要翻译：提供一种用于控制片上电压产生电路的电压输出变化的集成电路和方法。集成电路包括电压产生电路，其被配置为从提供的输入电压进行操作，并且在输出节点处产生不同于所提供的输入电压的片上电压。然后，电路块被布置成在电路块的操作期间接收由电压产生电路产生的片上电压源，该电路块在输出节点上呈现变化的负载。振荡电路还耦合到输出节点以在输出节点上提供额外的负载，并且被配置为产生其频率随着片上电压供应的值变化而变化的振荡信号。控制电路被配置为响应于触发条件来调节由振荡电路在输出节点上提供的附加负载。这提供了一种特别简单和有效的机制，用于在输出节点上提供额外的负载，其可以被改变，目的是抵消由电路块呈现的输出节点上的负载的变化，从而允许来自片上电压产生电路要被控制。

7. 发明授权

US6072349A Comparator 失效
标题翻译：比较器
公开(公告)号：US6072349A
公开(公告)日：2000-06-06
申请号：US001608
申请日：1997-12-31
申请人： Jack D. Pippin , Bal S. Sandhu
发明人： Jack D. Pippin , Bal S. Sandhu
IPC分类号： G06F1/20 , H03F3/45 , H03F3/72 , H03K5/24 , H03F1/02
CPC分类号： G06F1/324 , G06F1/20 , H03F3/45479 , H03F3/72 , H03K5/2481 , Y02B60/1217
摘要： A comparator includes an amplifier that has an offset voltage that is responsive to a level of current. A current source of the comparator is configured to be selectably enabled to adjust the level of the current to change the offset voltage.
摘要翻译：比较器包括具有响应于电流电平的偏移电压的放大器。比较器的电流源被配置为可选择地使能以调整电流的电平以改变偏移电压。

8. 发明授权

US5577001A High speed differential to single ended sense amplifier 失效
公开(公告)号：US5577001A
公开(公告)日：1996-11-19
申请号：US590489
申请日：1996-01-24
申请人： Bal S. Sandhu
发明人： Bal S. Sandhu
IPC分类号： G11C7/06 , G11C7/02
CPC分类号： G11C7/062
摘要： A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

9. 发明授权

US5359240A Low power digital signal buffer circuit 失效
标题翻译：低功耗数字信号缓冲电路
公开(公告)号：US5359240A
公开(公告)日：1994-10-25
申请号：US8165
申请日：1993-01-25
申请人： Bal S. Sandhu
发明人： Bal S. Sandhu
IPC分类号： H03K17/693 , H03K19/00 , H03K19/0185 , H03K19/096 , H03K19/20 , H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A low power signal buffer circuit for TTL signals includes a voltage reference controlled complementary MOSFET ("C-MOSFET") amplifier and a C-MOSFET inverter. The voltage reference controlled C-MOSFET amplifier receives a fixed reference voltage and a TTL input signal and provides a reference bias voltage. The C-MOSFET inverter has a pull-up P-type MOSFET which receives and is biased by the reference bias voltage, and a pull-down N-type MOSFET which receives the TTL input signal. The C-MOSFET inverter provides a TTL output signal with a substantially increased dynamic signal amplitude range. Current drain from the DC power supply for the buffer circuit decreases significantly as the TTL input signal state changes from "low" to "high" (e.g. logical "zero" to logical "one").
摘要翻译：用于TTL信号的低功率信号缓冲电路包括基准电压控制互补MOSFET（“C-MOSFET”）放大器和C-MOSFET反相器。电压基准控制C-MOSFET放大器接收固定的参考电压和TTL输入信号，并提供参考偏置电压。 C-MOSFET反相器具有接收并被参考偏置电压偏置的上拉型P型MOSFET，以及一个接收TTL输入信号的下拉式N型MOSFET。 C-MOSFET逆变器提供TTL输出信号，具有显着增加的动态信号幅度范围。由于TTL输入信号状态从“低”变为“高”（例如逻辑“0”变为逻辑“1”），缓冲电路的直流电源的电流消耗明显下降。

10. 发明授权

US5196739A High voltage charge pump 失效
标题翻译：高压充电泵
公开(公告)号：US5196739A
公开(公告)日：1993-03-23
申请号：US679702
申请日：1991-04-03
申请人： Bal S. Sandhu , Frederick K. Leung
发明人： Bal S. Sandhu , Frederick K. Leung
IPC分类号： G11C17/00 , G11C16/06 , H03K17/06 , H03K17/693
CPC分类号： H03K17/063 , H03K17/693
摘要： A charge pump circuit for use in Electrically Erasable Programmed Read-Only Memories in described herein. The charge pump uses a single clock signal, a voltage feedback arrangement to allow a D.C. voltage to pass a D.C. voltage, and a plurality of transistors, each transistor being coupled in series with each grounded-gate transistor, eliminating reverse-breakdown voltage loads on the grounded gate transistors.

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