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    • 5. 发明授权
    • System and method for scoping global nets in a hierarchical netlist
    • 在分层网表中对全局网进行范围划分的系统和方法
    • US5901064A
    • 1999-05-04
    • US692742
    • 1996-08-06
    • Larren Gene WeberRonald L. Taylor
    • Larren Gene WeberRonald L. Taylor
    • G06F17/50
    • G06F17/5022
    • A method and device for scoping nets from a schematic in a hierarchical netlist. The device is a complementary subsystem to a hierarchical netlister software package. The device allows instances or subcircuits in a schematic to systematically reassign (i.e., scope) local nets which represent global nets to other local nets so that the use of such nets does not affect usage of the global nets elsewhere in the circuit. The device tracks all global nets and maps the corresponding scoped nets to their net identifiers. Then, as the netlister creates the hierarchical netlist, the device replaces the global net's net identifier with the correct net identifier of the corresponding scoped net.
    • 一种用于从分层网表中的原理图界定网络的方法和设备。 该设备是分层网络软件包的补充子系统。 该装置允许原理图中的实例或子电路系统地将表示全局网络的局部网络重新分配(即范围)到其他局部网络,使得这种网络的使用不会影响电路中其他地方的全局网络的使用。 设备跟踪所有全局网络,并将相应的作用域网络映射到其网络标识符。 然后,当netlister创建分层网表时,设备将使用相应范围网的正确网标识替换全局网的净标识符。
    • 7. 发明授权
    • 256 Meg dynamic random access memory
    • 256 Meg动态随机存取存储器
    • US07969810B2
    • 2011-06-28
    • US12381143
    • 2009-03-06
    • Brent KeethLayne G. BunkerScott J. DemerRonald L TaylorJohn S. MullinRaymond J. BeffaFrank F. RossLarry D. Kinsman
    • Brent KeethLayne G. BunkerScott J. DemerRonald L TaylorJohn S. MullinRaymond J. BeffaFrank F. RossLarry D. Kinsman
    • G11C7/00
    • G11C5/063G11C5/025G11C5/145G11C5/147G11C11/401G11C11/4074G11C11/4076G11C11/4097G11C11/4099G11C29/021G11C29/028G11C29/12G11C29/12005G11C29/46G11C29/787G11C2029/0407H01L27/10805H01L2224/4826H01L2224/73215H01L2924/1305H01L2924/13091H01L2924/00
    • A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
    • 一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成,阵列被组织成32兆赫阵列阵列,它们被组织成64兆象限。 感测放大器位于各个阵列中的相邻行之间,而行解码器位于各个阵列中的相邻列之间。 在某些间隙单元中,提供多路复用器以将信号从I / O线传送到数据线。 提供了一种数据路径,除了上述之外,还包括阵列I / O块,响应于来自每个象限的数据,将数据输出到数据读取复用器,数据缓冲器和数据驱动器焊盘。 写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。 提供电源总线,其最小化外部提供的电压的路由,完全环绕每个阵列块,并且在每个阵列块内提供网格化的功率分配。 多个电压源提供阵列和外围电路中所需的电压。 电源组合以将其功率输出与功率需求相匹配,并保持所需的功率生产能力和去耦电容的比例。 提供上电序列电路以控制芯片的上电。 提供了冗余的行和列,就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。 芯片上还提供电路以支持各种类型的测试模式。