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1. 发明申请

US20090245009A1 256 Meg dynamic random access memory 有权
公开(公告)号：US20090245009A1
公开(公告)日：2009-10-01
申请号：US12381143
申请日：2009-03-06
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

2. 发明申请

US20110261628A1 256 Meg dynamic random access memory 失效
公开(公告)号：US20110261628A1
公开(公告)日：2011-10-27
申请号：US13135066
申请日：2011-06-24
申请人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Scott J. Demer , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

3. 发明授权

US06314011B1 256 Meg dynamic random access memory 失效
标题翻译： 256 Meg动态随机存取存储器
公开(公告)号：US06314011B1
公开(公告)日：2001-11-06
申请号：US08916692
申请日：1997-08-22
申请人： Brent Keeth , Layne G. Bunker , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
发明人： Brent Keeth , Layne G. Bunker , Ronald L. Taylor , John S. Mullin , Raymond J. Beffa , Frank F. Ross , Larry D. Kinsman
IPC分类号： G11C502
CPC分类号： H01L27/10805
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。感测放大器位于各个阵列中的相邻行之间，而行解码器位于各个阵列中的相邻列之间。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括用于向阵列I / O块提供数据的缓冲器和数据写入多路复用器中的数据。提供电源总线，其最小化外部提供的电压的路由，完全环绕每个阵列块，并且在每个阵列块内提供网格化的功率分配。多个电压源提供阵列和外围电路中所需的电压。电源组合以将其功率输出与功率需求相匹配，并保持所需的功率生产能力和去耦电容的比例。提供上电序列电路以控制芯片的上电。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

4. 发明授权

US06452825B1 256 meg dynamic random access memory having a programmable multiplexor 有权
标题翻译：具有可编程多路复用器的256兆赫动态随机存取存储器
公开(公告)号：US06452825B1
公开(公告)日：2002-09-17
申请号：US09615496
申请日：2000-07-13
申请人： Brent Keeth , Layne G. Bunker , Ronald L. Taylor , John S. Mullin
发明人： Brent Keeth , Layne G. Bunker , Ronald L. Taylor , John S. Mullin
IPC分类号： G11C502
CPC分类号： G11C5/063 , G11C5/025 , G11C5/145 , G11C5/147 , G11C11/401 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C11/4099 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/12005 , G11C29/46 , G11C29/787 , G11C2029/0407 , H01L27/10805 , H01L2224/4826 , H01L2224/73215 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexors are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data writes muxes for providing data to the array I/O blocks. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
摘要翻译：一个256兆赫动态随机存取存储器由组成单独阵列的多个单元组成，阵列被组织成32兆赫阵列阵列，它们被组织成64兆象限。在某些间隙单元中，提供多路复用器以将信号从I / O线传送到数据线。提供了一种数据路径，除了上述之外，还包括阵列I / O块，响应于每个象限的数据，将数据输出到数据读取多路复用器，数据缓冲器和数据驱动器焊盘。写数据路径包括缓冲区中的数据和数据写入多路复用器，用于向阵列I / O块提供数据。提供了冗余的行和列，就像使用操作行和列逻辑地替换有缺陷的行和列所需的电路一样。芯片上还提供电路以支持各种类型的测试模式。

5. 发明授权

US5901064A System and method for scoping global nets in a hierarchical netlist 失效
标题翻译：在分层网表中对全局网进行范围划分的系统和方法
公开(公告)号：US5901064A
公开(公告)日：1999-05-04
申请号：US692742
申请日：1996-08-06
申请人： Larren Gene Weber , Ronald L. Taylor
发明人： Larren Gene Weber , Ronald L. Taylor
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and device for scoping nets from a schematic in a hierarchical netlist. The device is a complementary subsystem to a hierarchical netlister software package. The device allows instances or subcircuits in a schematic to systematically reassign (i.e., scope) local nets which represent global nets to other local nets so that the use of such nets does not affect usage of the global nets elsewhere in the circuit. The device tracks all global nets and maps the corresponding scoped nets to their net identifiers. Then, as the netlister creates the hierarchical netlist, the device replaces the global net's net identifier with the correct net identifier of the corresponding scoped net.
摘要翻译：一种用于从分层网表中的原理图界定网络的方法和设备。该设备是分层网络软件包的补充子系统。该装置允许原理图中的实例或子电路系统地将表示全局网络的局部网络重新分配（即范围）到其他局部网络，使得这种网络的使用不会影响电路中其他地方的全局网络的使用。设备跟踪所有全局网络，并将相应的作用域网络映射到其网络标识符。然后，当netlister创建分层网表时，设备将使用相应范围网的正确网标识替换全局网的净标识符。

6. 发明授权

US5946218A System and method for changing the connected behavior of a circuit design schematic 有权
标题翻译：改变电路设计原理图的连接行为的系统和方法
公开(公告)号：US5946218A
公开(公告)日：1999-08-31
申请号：US145734
申请日：1998-09-02
申请人： Ronald L. Taylor , Larren Gene Weber
发明人： Ronald L. Taylor , Larren Gene Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for changing the connected behavior of a circuit design schematic at the time a netlist is being created by assigning instance parameters to each switch instance, the parameter having a value representing that the position of the switch is open or closed, the parameter being evaluated at the time the netlist is created to determine the position of the switch. When the netlist being created is a flat netlist, a closed switch condition is represented by printing information to the netlist file that identifies the nets being interconnected. When the netlist being created is a hierarchical netlist, the nets being interconnected are declared as "artificial" ports, allowing these nets to be tracked through the hierarchy to instances at which the parameters are evaluated and to provide a connection between these nets, allowing the interconnection of nets to be specified at a level in the hierarchy other than that at which the switch is declared.
摘要翻译：一种用于通过向每个交换机实例分配实例参数来创建网表时改变电路设计原理图的连接行为的方法和系统，该参数具有表示交换机的位置打开或关闭的值，该参数在创建网表时进行评估，以确定交换机的位置。当创建的网表是平面网表时，通过将网络列表文件打印到标识要互连的网络的网表来表示封闭的切换条件。当创建的网表是分层网表时，被互连的网络被声明为“人造”端口，允许这些网络通过层次结构跟踪参数被评估的实例，并且在这些网络之间提供连接，允许要在指定交换机所在层次结构中的级别指定网络的互连。

7. 发明授权

US5815402A System and method for changing the connected behavior of a circuit design schematic 失效
公开(公告)号：US5815402A
公开(公告)日：1998-09-29
申请号：US660110
申请日：1996-06-07
申请人： Ronald L. Taylor , Larren Gene Weber
发明人： Ronald L. Taylor , Larren Gene Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for changing the connected behavior of a circuit design schematic at the time a netlist is being created by assigning instance parameters to each switch instance, the parameter having a value representing that the position of the switch is open or closed, the parameter being evaluated at the time the netlist is created to determine the position of the switch. When the netlist being created is a flat netlist, a closed switch condition is represented by printing information to the netlist file that identifies the nets being interconnected. When the netlist being created is a hierarchical netlist, the nets being interconnected are declared as "artificial" ports, allowing these nets to be tracked through the hierarchy to instances at which the parameters are evaluated and to provide a connection between these nets, allowing the interconnection of nets to be specified at a level in the hierarchy other than that at which the switch is declared.

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