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1. 发明授权

US06593200B2 Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation 有权
标题翻译：在具有浅沟槽隔离的平坦化工艺中形成集成电感器和高速互连的方法
公开(公告)号：US06593200B2
公开(公告)日：2003-07-15
申请号：US09989649
申请日：2001-11-20
申请人： Alexander Kalnitsky , Dmitri A. Choutov , Geoffrey C. Stutzin , Robert F. Scheer
发明人： Alexander Kalnitsky , Dmitri A. Choutov , Geoffrey C. Stutzin , Robert F. Scheer
IPC分类号： H01L21331
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and ‘cross-talk’ between conductors are substantially reduced. The resulting semiconductor device is also disclosed.
摘要翻译：一种形成具有电感器和/或高速互连的半导体器件的方法。该方法包括在衬底上形成外延层，形成穿过外延层的开口以暴露衬底的下部区域，在外延层的开口内形成第一电介质材料，使第一电介质层平坦化，形成第二电介质材料层，然后在外延层的开口上方的第二介电材料层上形成金属化电感器。在这种情况下，由于电感器和高速互连不会覆盖在导电外延层上，电感器的Q因子的劣化，高速互连的损耗特性和导体之间的“串扰”大大降低还公开了所得到的半导体器件。

2. 发明授权

US06855585B1 Integrating multiple thin film resistors 有权
标题翻译：集成多个薄膜电阻
公开(公告)号：US06855585B1
公开(公告)日：2005-02-15
申请号：US10002429
申请日：2001-10-31
申请人： Alexander Kalnitsky , Joseph Paul Elull , Ralph Wall , Robert F. Scheer , Jonathan Herman , Glenn Nobinger , Viktor Zekeriya
发明人： Alexander Kalnitsky , Joseph Paul Elull , Ralph Wall , Robert F. Scheer , Jonathan Herman , Glenn Nobinger , Viktor Zekeriya
IPC分类号： H01L27/01 , H01L27/08 , H01L21/302
CPC分类号： H01L27/0802 , H01L27/016
摘要： A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.
摘要翻译：一种在衬底上形成多个电阻器的方法。该方法最初包括在衬底上提供第一电阻器。在第一电阻器上沉积，图案化和选择性蚀刻第一电介质层。第二电阻材料设置在第一介电层上。此外，着陆垫材料设置在第二电阻材料上。然后选择性地蚀刻着陆焊盘材料和第二电阻材料。选择性蚀刻在第一区域中形成用于第一电阻器的触点，并且在第二区域中形成第二电阻器和相关联的触点。

3. 发明授权

US06686250B1 Method of forming self-aligned bipolar transistor 失效
标题翻译：形成自对准双极晶体管的方法
公开(公告)号：US06686250B1
公开(公告)日：2004-02-03
申请号：US10300105
申请日：2002-11-20
申请人： Alexander Kalnitsky , Michael Rowlandson , Fanling H. Yang , Sang Park , Robert F. Scheer
发明人： Alexander Kalnitsky , Michael Rowlandson , Fanling H. Yang , Sang Park , Robert F. Scheer
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.
摘要翻译：提供自对准双极晶体管及其形成方法。双极晶体管具有由双层多晶硅形成的由y形结构表征的发射极区域。双层多晶硅包括第一多晶硅发射极结构和第二多晶硅发射极结构。形成双极晶体管的方法包括在衬底上形成发射极叠层。发射极堆叠包括第一多晶硅发射极结构和插塞结构。发射极堆叠将衬底限定为掩模部分并暴露于相邻部分。暴露的相邻部分被选择性掺杂掺杂剂以限定非本征基区，其中掺杂剂被阻止进入掩蔽部分。在选择性地掺杂非本征基极区域之后，将插塞结构从发射极堆叠移除，并且第二多晶硅发射极结构形成在第一多晶硅发射极结构上以限定双极晶体管的发射极区域。

4. 发明授权

US06861324B2 Method of forming a super self-aligned hetero-junction bipolar transistor 有权
标题翻译：形成超自对准异质结双极晶体管的方法
公开(公告)号：US06861324B2
公开(公告)日：2005-03-01
申请号：US09882538
申请日：2001-06-15
申请人： Alexander Kalnitsky , Michael Rowlandson , Ken Liao , Robert F. Scheer
发明人： Alexander Kalnitsky , Michael Rowlandson , Ken Liao , Robert F. Scheer
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The present invention provides a method of forming a super self-aligned bipolar transistor with enhanced electrical characteristics. The power gain and frequency response of the transistor are improved by horizontally etching an area for the base region that is wider than the active emitter and collector regions. By removing polysilicon layers within the device, the base region resistance goes down and unwanted capacitive effects are reduced.
摘要翻译：本发明提供一种形成具有增强的电特性的超自对准双极晶体管的方法。通过水平蚀刻比有源发射极和集电极区域宽的基极区域的区域来提高晶体管的功率增益和频率响应。通过去除器件内的多晶硅层，基极区电阻下降，不必要的电容效应降低。

5. 发明授权

US06489217B1 Method of forming an integrated circuit on a low loss substrate 失效
标题翻译：在低损耗基板上形成集成电路的方法
公开(公告)号：US06489217B1
公开(公告)日：2002-12-03
申请号：US09900848
申请日：2001-07-03
申请人： Alexander Kalnitsky , Robert F. Scheer
发明人： Alexander Kalnitsky , Robert F. Scheer
IPC分类号： H01L2176
CPC分类号： H01L21/84 , H01L27/12 , Y10S438/96
摘要： A method for manufacturing an integrated circuit structure is disclosed. The method includes providing a layer of porous silicon, and epitaxially growing a high resistivity layer on the layer of porous silicon. Devices are then formed on the high resistivity layer to produce the integrated circuit structure. The integrated circuit structure is attached to a silica substrate, such that the silica substrate is coupled to the devices. Further, surface contacts are provided on the structure. The layer of porous silicon is then removed.
摘要翻译：公开了一种用于制造集成电路结构的方法。该方法包括提供多孔硅层，并在多孔硅层上外延生长高电阻率层。然后在高电阻率层上形成器件以产生集成电路结构。集成电路结构附接到二氧化硅衬底，使得二氧化硅衬底耦合到器件。此外，在结构上提供表面接触。然后去除多孔硅层。

6. 发明授权

US06303413B1 Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates 有权
标题翻译：形成适用于绝缘体上硅（SOI）衬底的浅和深沟槽隔离（SDTI）的方法
公开(公告)号：US06303413B1
公开(公告)日：2001-10-16
申请号：US09564178
申请日：2000-05-03
申请人： Alexander Kalnitsky , Dmitri A. Choutov , Robert F. Scheer , Fanling H. Yang , Thomas W. Dobson , Tadanori Yamaguchi , Geoffrey C. Stutzin , Ken Liao
发明人： Alexander Kalnitsky , Dmitri A. Choutov , Robert F. Scheer , Fanling H. Yang , Thomas W. Dobson , Tadanori Yamaguchi , Geoffrey C. Stutzin , Ken Liao
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286
摘要： A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.
摘要翻译：提供了形成浅深沟槽隔离（SDTI）的方法，其包括以下步骤：通过绝缘体上硅（SOI）层形成一对深沟槽，而不会基本上干扰下面的掩埋氧化物（BOX）层。一旦形成了深沟槽，则沟槽用合适的电绝缘材料（例如未掺杂的多晶硅或电介质材料）放置并且被回蚀以获得基本平坦化的顶表面。随后，在平坦化的顶表面上沉积活性氮化物层，然后形成一对浅沟槽。使用低选择性蚀刻来形成浅沟槽以均匀蚀刻深沟槽衬垫氧化物，SOI层和电绝缘材料，其具有相对于蚀刻方向以非垂直角度的界面。一旦形成浅沟槽和深沟槽，就可以执行包括填充浅沟槽，退火和化学机械抛光的后续处理。

7. 发明授权

US07026666B2 Self-aligned NPN transistor with raised extrinsic base 有权
公开(公告)号：US07026666B2
公开(公告)日：2006-04-11
申请号：US10734928
申请日：2003-12-12
申请人： Alexander Kalnitsky , Alexel Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
发明人： Alexander Kalnitsky , Alexel Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/1004 , H01L29/7378
摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

8. 发明授权

US06767798B2 Method of forming self-aligned NPN transistor with raised extrinsic base 有权
标题翻译：形成具有凸起外在基极的自对准NPN晶体管的方法
公开(公告)号：US06767798B2
公开(公告)日：2004-07-27
申请号：US10119594
申请日：2002-04-09
申请人： Alexander Kalnitsky , Alexei Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
发明人： Alexander Kalnitsky , Alexei Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/1004 , H01L29/7378
摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.
摘要翻译：提供自对准双极晶体管及其形成方法。双极晶体管具有凸起的外在基极，使得通过提供比本征基底更厚的外在基极来降低连接基极电阻。外部基极的厚度的增加提供了重掺杂基极区域的较小电阻层。形成双极晶体管的方法包括在衬底上沉积第一外延层以形成具有本征基极区域和非本征基极区域的基极区域。通过在第一外延层的一部分上沉积第二外延层使外部基极层的厚度为x，并且本征层的厚度为y，其中x> y，凸起外部基极区域。使用化学气相外延装置沉积第二外延层，其中Ge至Si的浓度在外延过程中从高于5％逐渐降低至接近0％。因此，第二外延层在第一和第二外延层的界面附近具有最高的Ge浓度。在第二外延区域的顶面，Ge的浓度逐渐降低到接近0％。

9. 发明授权

US06492237B2 Method of forming an NPN device 失效
标题翻译：形成NPN器件的方法
公开(公告)号：US06492237B2
公开(公告)日：2002-12-10
申请号：US09782820
申请日：2001-02-12
申请人： Alexander Kalnitsky , Sang Hoon Park , Robert F. Scheer
发明人： Alexander Kalnitsky , Sang Hoon Park , Robert F. Scheer
IPC分类号： H01L21331
CPC分类号： H01L29/66287
摘要： A method of forming an NPN semiconductor device includes the steps of forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate etching of the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices. As an option, after the opening of the oxide-nitride-oxide stack is formed, a local oxidation of silicon (LOCOS) and etched can be preformed to create oxide spacers to line the opening wall above the base region.
摘要翻译：形成NPN半导体器件的方法包括以下步骤：在衬底内形成集电极区域，在集电极区域上形成基极区域，并在基极区域上形成氧化物 - 氮化物 - 氧化物堆叠体。一旦形成这三个结构，就通过氧化物 - 氧化物 - 氧化物堆叠形成一个开口，露出基极区域的顶面。然后，使用掺杂多晶硅材料来填充开口并与基极区域电接触。通过对开口的适当蚀刻来使用氧化物 - 氮化物 - 氧化物堆叠消除了基底区域对用于形成NPN半导体器件的现有技术方法的典型的反应离子蚀刻环境的曝光。作为选择，在形成氧化物 - 氮化物 - 氧化物堆叠的打开之后，可以预先形成硅（LOCOS）的局部氧化并蚀刻以形成氧化物间隔物以使基部区域上方的开口壁成线。

10. 发明授权

US06475873B1 Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology 有权
标题翻译：在全平面化集成电路技术中形成激光可调薄膜电阻的方法
公开(公告)号：US06475873B1
公开(公告)日：2002-11-05
申请号：US09631581
申请日：2000-08-04
申请人： Alexander Kalnitsky , Robert F. Scheer , Joseph P. Ellul
发明人： Alexander Kalnitsky , Robert F. Scheer , Joseph P. Ellul
IPC分类号： H01L2120
CPC分类号： H01L28/24 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor. More specifically, the method of forming a thin film resistor includes the steps of forming a pair of spaced-apart polysilicon islands over a semiconductor substrate, forming a dielectric layer over and between the polysilicon islands, forming contact holes through the dielectric layer to expose respective first regions of the polysilicon islands, forming a layer of thin film resistive material that extends between respective first regions of the polysilicon islands, forming another dielectric layer over the polysilicon islands and over the thin film resistive material layer, and forming metal contacts through the second dielectric layer in a manner that they make contact to respective second regions of the polysilicon islands, wherein the first and second regions of the polysilicon islands are different.
摘要翻译：本文提供了一种新的和改进的形成薄膜电阻器的方法，其克服了现有技术方法的许多缺点。更具体地，形成薄膜的新方法提供了薄膜电阻下的良好控制的电介质厚度，其对于激光修整目的是有用的。电介质层的优选厚度是用于激光修整电阻器的光能的四分之一波长的整数。该新方法还提供了不直接接触薄膜电阻器的薄膜电阻器的接触，以防止对薄膜电阻器的任何不利的处理效果。更具体地，形成薄膜电阻器的方法包括以下步骤：在半导体衬底上形成一对间隔开的多晶硅岛，在多晶硅岛之上和之间形成电介质层，形成通过电介质层的接触孔，以暴露出相应的形成多晶硅岛的第一区域，形成薄膜电阻材料层，其在多晶硅岛的相应的第一区之间延伸，在多晶硅岛上方和薄膜电阻材料层上方形成另一介电层，并通过第二区形成金属接触电介质层，使得它们与多晶硅岛的相应第二区接触，其中多晶硅岛的第一和第二区不同。

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