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1. 发明授权

US07260810B2 Method of extracting properties of back end of line (BEOL) chip architecture 失效
标题翻译：提取后端（BEOL）芯片架构性能的方法
公开(公告)号：US07260810B2
公开(公告)日：2007-08-21
申请号：US10687475
申请日：2003-10-16
申请人： Ronald G. Filippi, Jr. , Giovanni Fiorenza , Xiao Hu Liu , Conal Eugene Murray , Gregory Allen Northrop , Thomas M. Shaw , Richard Andre′ Wachnik , Mary Yvonne Lanzerotti Wisniewski
发明人： Ronald G. Filippi, Jr. , Giovanni Fiorenza , Xiao Hu Liu , Conal Eugene Murray , Gregory Allen Northrop , Thomas M. Shaw , Richard Andre′ Wachnik , Mary Yvonne Lanzerotti Wisniewski
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G06F17/5018
摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
摘要翻译：用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。然后，由于设计中的局部属性，确定了设计的响应。

2. 发明申请

US20090200642A1 HIGHLY TUNABLE METAL-ON-SEMICONDUCTOR TRENCH VARACTOR 有权
标题翻译：高可控金属 - 半导体TRENCH变压器
公开(公告)号：US20090200642A1
公开(公告)日：2009-08-13
申请号：US12028145
申请日：2008-02-08
申请人： Randy W. Mann , Jae-Eun Park , Richard Andre Wachnik
发明人： Randy W. Mann , Jae-Eun Park , Richard Andre Wachnik
IPC分类号： H01L29/93
CPC分类号： H01L29/93
摘要： An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.
摘要翻译：在半导体衬底的掺杂部分中形成深沟槽阵列，形成下电极。在深沟槽阵列的侧壁上形成介电层。深沟槽阵列用掺杂半导体材料填充以形成上电极，其包括顶板部分和多个延伸部分到沟槽阵列中。在耗尽模式中，跨越电介质层的偏置条件消耗顶部电极内的多数载流子，从而提供低电容。在累积模式中，偏置条件吸引多数载流子朝向电介质层，提供高电容。因此，沟槽金属氧化物半导体（MOS）变容二极管根据偏压的极性提供可变电容。

3. 发明授权

US07217978B2 SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same 有权
标题翻译： SRAM存储器和微处理器具有实现在高性能硅衬底中的逻辑部分和具有连接体的场效应晶体管的SRAM阵列部分及其制造方法
公开(公告)号：US07217978B2
公开(公告)日：2007-05-15
申请号：US11038593
申请日：2005-01-19
申请人： Rajiv V. Joshi , Richard Andre Wachnik , Yue Tan , Kerry Bernstein
发明人： Rajiv V. Joshi , Richard Andre Wachnik , Yue Tan , Kerry Bernstein
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0207 , H01L27/1104
摘要： The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions. Another aspect of this invention concerns a microprocessor fabricated on an hybrid orientation substrate where the logic portion of the circuit has NFETs fabricated in (100) crystal orientation SOI silicon regions with floating body regions and PFETs fabricated in (110) crystal orientation bulk silicon regions; and where the SRAM memory portion has NFETs fabricated in (100) crystal orientation SOI silicon regions with body regions linked by leakage path diffusion regions beneath shallow source/drain diffusions and PFETs fabricated in (110) crystal orientation silicon regions.
摘要翻译：本发明一般涉及用于存储器电路的制造方法和器件架构，更具体地说，涉及用于存储器电路的混合绝缘体上硅（SOI）和批量结构。本发明的一个方面涉及SRAM SRAM单元结构，其中SRAM单元中的至少一对相邻NFET具有通过位于浅源/漏扩散之下的泄漏路径扩散区连接的体区，其中泄漏路径扩散区从底部延伸源极/漏极扩散到掩埋氧化物层的至少一对NFET，以及来自相邻SRAM单元的至少一对NFET，其具有通过相邻的源极/漏极扩散附近的相似泄漏路径扩散区域连接的体区。本发明的另一方面涉及一种制造在混合取向基板上的微处理器，其中该电路的逻辑部分具有在具有浮动体区域的（100）晶体取向SOI硅区域和在（110）晶体取向体硅区域中制造的PFET）制造的NFET。并且其中SRAM存储器部分具有在（100）晶体取向SOI硅区域中制造的NFET，其中主体区域通过在（110）晶体取向硅区域中制造的浅源/漏扩散下的泄漏路径扩散区域和PFET连接。

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