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1. 发明申请

US20080013671A1 Frequency Division by Odd Integers 审中-公开
标题翻译：频率分为奇数整数
公开(公告)号：US20080013671A1
公开(公告)日：2008-01-17
申请号：US11718801
申请日：2005-11-09
申请人： Remco Van De Beek , Dominicus Leenaerts
发明人： Remco Van De Beek , Dominicus Leenaerts
IPC分类号： H03K23/48
CPC分类号： H03K23/483
摘要： The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CL1) frequency by an odd integer. A digital value is shifted into a set of latches based on the clock signal (CL1) and kept there a predetermined number of half clock cycles. The value is shifted into a following latch delayed with half a clock cycle of the clock signal compared with a previous latch. Then a first (Q1) and a second (Q6) intermediate signal, each provided through information stored in a latch, are interpolated for forming said first output signal (O Q). Because of this it is possible to provide an output signal having edges displaced from clock signal edges, thus allowing a higher resolution than the original clock signal has and in particular, enabling quadrature outputs from a standard odd-integer frequency divider.
摘要翻译：本发明涉及一种用于提供具有通过将时钟信号（CL 1）频率除以奇整数而获得的频率的至少第一输出信号（O Q）的方法和装置。数字值根据时钟信号（CL 1）移入一组锁存器，并保持预定数量的半个时钟周期。与先前的锁存器相比，该值被移位到延迟了时钟信号的半个时钟周期的后续锁存器。然后插入通过存储在锁存器中的信息提供的第一（Q 1）和第二（Q 6）中间信号，以形成所述第一输出信号（O Q）。因此，可以提供具有从时钟信号边缘移位的边缘的输出信号，从而允许比原始时钟信号具有更高的分辨率，并且特别地，允许来自标准奇整数分频器的正交输出。

2. 发明申请

US20060164137A1 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US20060164137A1
公开(公告)日：2006-07-27
申请号：US10525862
申请日：2003-07-31
申请人： Remco Van De Beek , Eric Klumperink , Bram Nauta , Cicero Vaucher
发明人： Remco Van De Beek , Eric Klumperink , Bram Nauta , Cicero Vaucher
IPC分类号： H03L7/06
CPC分类号： H03L7/191 , H03D13/00 , H03L7/087 , H03L7/089 , H03L7/0893 , H03L7/113
摘要： A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).
摘要翻译：一种锁相环，包括用于确定参考信号（Ref）和相互相移信号（I，Q）之间的相位差的相位检测器（100），以产生频率控制信号（U，D），相位检测器（100）包括：用于通过参考信号（Ref）和相对相移信号（I，Q）之一的二进制相乘来获得所述频率控制信号（U，D）中的第一个的装置（10）。以及用于通过相对相移信号（I，Q）的二进制相乘来获得所述频率控制信号（U，D）中的第二个的装置（20）。

3. 发明申请

US20140038534A1 HARMONIC SUPPRESSION IN SWITCHING AMPLIFIERS 有权
标题翻译：谐波抑制在开关放大器
公开(公告)号：US20140038534A1
公开(公告)日：2014-02-06
申请号：US13564013
申请日：2012-08-01
申请人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
发明人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
IPC分类号： H03C1/52
CPC分类号： H03C5/00 , H03F3/2173 , H03F3/24 , H04L25/0272
摘要： Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.
摘要翻译：考虑到具有两个产生具有引入的谐波的差分输出信号的D类开关放大器的射频（RF）发射机电路中的谐波的可配置抑制。选择的谐波用于确定持续时间。谐波抑制电路修正使用振幅分量和相位分量编码的射频极调制数据信号。修改响应于所确定的持续时间。开关功率放大器放大经修改的极化调制数据信号以产生放大信号。放大的信号包括三个信号电平，高信号电平，中间信号电平和低信号电平。高信号和低信号电平之间的转换时序表示相位分量，并且转换包括持续时间的中间信号电平，从而抑制所选择的谐波。

4. 发明授权

US08571093B1 Communication interface for galvanic isolation 有权
标题翻译：电隔离通讯接口
公开(公告)号：US08571093B1
公开(公告)日：2013-10-29
申请号：US13454654
申请日：2012-04-24
申请人： Remco Van de Beek
发明人： Remco Van de Beek
IPC分类号： H04B1/38
CPC分类号： H04L25/0266
摘要： In one or more embodiments, a system is provided for communicating between different voltage domains using N+1 capacitive-coupled conductive lines to provide N communication channels. For instance, bi-directional communication (e.g., a first communication in a first direction and a second communication path in the opposite direction) may be provided using three capacitive-coupled signal paths. Two of the signal paths are used as single-ended (i.e., non-differential) signal paths. The third signal path is used to suppress voltage disturbances between two voltage domains.
摘要翻译：在一个或多个实施例中，提供一种用于使用N + 1个电容耦合导线在不同电压域之间通信以提供N个通信信道的系统。例如，可以使用三个电容耦合信号路径来提供双向通信（例如，在第一方向上的第一通信和相反方向上的第二通信路径）。两条信号路径用作单端（即非差分）信号路径。第三信号路径用于抑制两个电压域之间的电压干扰。

5. 发明申请

US20110019773A1 SIGNAL PROCESSING CIRCUIT AND METHOD WITH FREQUENCY UP-AND DOWN-CONVERSION 有权
标题翻译：信号处理电路和频率上下转换的方法
公开(公告)号：US20110019773A1
公开(公告)日：2011-01-27
申请号：US12735201
申请日：2008-12-19
申请人： Remco Van De Beek , Domine Leenaerts , Charles Razzell , Jozef R. Ervoet
发明人： Remco Van De Beek , Domine Leenaerts , Charles Razzell , Jozef R. Ervoet
IPC分类号： H04L27/06
CPC分类号： H03D7/00 , H03D2200/0047 , H03D2200/0082 , H04L5/0007 , H04L27/0014 , H04L27/227 , H04L27/2601 , H04L27/364 , H04L2027/0016 , H04L2027/0022 , H04L2027/0032 , H04L2027/0065
摘要： A signal processing circuit comprises a frequency up-conversion circuit (14, 60) for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit (16) for performing down-conversion with a second local oscillator frequency. A digital signal processor (10) controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor (10) switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor (10) measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.
摘要翻译：信号处理电路包括用于以第一本地振荡器频率执行上变频的升频转换电路（14,60）和用于执行具有第二本机振荡器频率的下变频的降频转换电路（16）。数字信号处理器（10）控制向上转换电路提供表示第一复信号的第一信号，并接收表示第二复信号的第二信号。数字信号处理器控制上转换和/或下转换结果的I / Q不匹配的补偿。数字信号处理器（10）切换到用于选择所述补偿的参数的校准模式。在校准模式中，第一和第二本地振荡器频率相对于彼此具有频率偏移。数字信号处理器（10）以对应于上变频和/或下变频结果中的一个且不超过一个失配的频率测量频率分量的幅度，并且根据幅度选择参数。

6. 发明授权

US09172329B2 Harmonic suppression in switching amplifiers 有权
标题翻译：开关放大器谐波抑制
公开(公告)号：US09172329B2
公开(公告)日：2015-10-27
申请号：US13564013
申请日：2012-08-01
申请人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
发明人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
IPC分类号： H03F3/217 , H03F1/32 , H03C5/00 , H03F3/24 , H04L25/02
CPC分类号： H03C5/00 , H03F3/2173 , H03F3/24 , H04L25/0272
摘要： Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.
摘要翻译：考虑到具有两个产生具有引入的谐波的差分输出信号的D类开关放大器的射频（RF）发射机电路中的谐波的可配置抑制。选择的谐波用于确定持续时间。谐波抑制电路修正使用振幅分量和相位分量编码的射频极调制数据信号。修改响应于所确定的持续时间。开关功率放大器放大经修改的极化调制数据信号以产生放大信号。放大的信号包括三个信号电平，高信号电平，中间信号电平和低信号电平。高信号和低信号电平之间的转换时序表示相位分量，并且转换包括持续时间的中间信号电平，从而抑制所选择的谐波。

7. 发明授权

US08532224B2 Signal processing circuit and method with frequency up- and down-conversion 有权
标题翻译：具有上变频和下变频的信号处理电路及方法
公开(公告)号：US08532224B2
公开(公告)日：2013-09-10
申请号：US12735201
申请日：2008-12-19
申请人： Remco Van De Beek , Domine Leenaerts , Charles Razzell , Jozef R. M. Ervoet
发明人： Remco Van De Beek , Domine Leenaerts , Charles Razzell , Jozef R. M. Ervoet
IPC分类号： H03C3/00
CPC分类号： H03D7/00 , H03D2200/0047 , H03D2200/0082 , H04L5/0007 , H04L27/0014 , H04L27/227 , H04L27/2601 , H04L27/364 , H04L2027/0016 , H04L2027/0022 , H04L2027/0032 , H04L2027/0065
摘要： A signal processing circuit comprises a frequency up-conversion circuit (14, 60) for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit (16) for performing down-conversion with a second local oscillator frequency. A digital signal processor (10) controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor (10) switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor (10) measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.
摘要翻译：信号处理电路包括用于以第一本地振荡器频率执行上变频的升频转换电路（14,60）和用于执行具有第二本机振荡器频率的下变频的降频转换电路（16）。数字信号处理器（10）控制向上转换电路提供表示第一复信号的第一信号，并接收表示第二复信号的第二信号。数字信号处理器控制上转换和/或下转换结果的I / Q不匹配的补偿。数字信号处理器（10）切换到用于选择所述补偿的参数的校准模式。在校准模式中，第一和第二本地振荡器频率相对于彼此具有频率偏移。数字信号处理器（10）以对应于上变频和/或下变频结果中的一个且不超过一个失配的频率测量频率分量的幅度，并且根据幅度选择参数。

8. 发明申请

US20130279549A1 COMMUNICATION INTERFACE FOR GALVANIC ISOLATION 有权
标题翻译：沟通隔离通信接口
公开(公告)号：US20130279549A1
公开(公告)日：2013-10-24
申请号：US13454654
申请日：2012-04-24
申请人： Remco Van de Beek
发明人： Remco Van de Beek
IPC分类号： H04B1/38
CPC分类号： H04L25/0266
摘要： In one or more embodiments, a system is provided for communicating between different voltage domains using N+1 capacitive-coupled conductive lines to provide N communication channels. For instance, bi-directional communication (e.g., a first communication in a first direction and a second communication path in the opposite direction) may be provided using three capacitive-coupled signal paths. Two of the signal paths are used as single-ended (i.e., non-differential) signal paths. The third signal path is used to suppress voltage disturbances between two voltage domains.
摘要翻译：在一个或多个实施例中，提供一种用于使用N + 1个电容耦合导线在不同电压域之间通信以提供N个通信信道的系统。例如，可以使用三个电容耦合信号路径来提供双向通信（例如，在第一方向上的第一通信和相反方向上的第二通信路径）。两条信号路径用作单端（即非差分）信号路径。第三信号路径用于抑制两个电压域之间的电压扰动。

9. 发明申请

US20070257737A1 Device for Ultra Wide Band Frequency Generating 失效
标题翻译：超宽频带发生装置
公开(公告)号：US20070257737A1
公开(公告)日：2007-11-08
申请号：US11574916
申请日：2005-09-05
申请人： Remco Van De Beek , Dominicus Leenaerts , Gerard Van Der Weide , Jozef Bergervoet
发明人： Remco Van De Beek , Dominicus Leenaerts , Gerard Van Der Weide , Jozef Bergervoet
IPC分类号： H03B1/00
CPC分类号： H03D3/009
摘要： Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46). Such frequency selectors (45) comprise multiplexers (126,127) for supplying the second inphase/quadrature oscillation signals, with a combination of these second oscillation signals corresponding with a positive frequency, a negative frequency or a zero frequency, and comprise coders (125) for controlling the multiplexers (126,127).
摘要翻译：用于交换超宽带信号的装置（1）包括用于频率转换信号的频率转换级（20,30）和用于将主相位/正交振荡信号提供给频率转换级（20,30）的振荡级（40）。通过为振荡级（40）提供多相滤波器（43,44）以减少振荡信号中的谐波，主振荡信号将足够清洁。振荡级（40）包括用于将第一同相/正交振荡信号和第二同相/正交振荡信号转换成主振荡信号的混频器（46）。多相过滤器（43,44）可以位于混合器（46）之前和之后。频率选择器（45）代替位于混频器（46）之后的现有技术的多路复用器。这种频率选择器（45）包括用于提供第二同相/正交振荡信号的多路复用器（126,127）以及与正频率，负频率或零频率对应的这些第二振荡信号的组合，并且包括编码器（125），用于控制多路复用器（126,127）。

10. 发明申请

US20050084051A1 Phase-locked-loop with reduced clock jitter 有权
标题翻译：锁相环减少时钟抖动
公开(公告)号：US20050084051A1
公开(公告)日：2005-04-21
申请号：US10503187
申请日：2003-01-20
申请人： Bram Nauta , Remco Van De Beek , Cicero Vaucher
发明人： Bram Nauta , Remco Van De Beek , Cicero Vaucher
IPC分类号： H03L7/18 , H03L7/089 , H03L7/095 , H03L7/107 , H03L7/197 , H03D3/24
CPC分类号： H03L7/095 , H03L7/0891 , H03L7/107 , H03L7/197
摘要： The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
摘要翻译：锁相环（PLL）电路及其控制方法技术领域本发明涉及锁相环（PLL）电路和控制这种PLL电路的方法，其中输入参考信号的频率和从输出振荡信号导出的反馈信号的频率除以从而降低PLL电路的相位检测装置（1）的频率。响应于PLL电路的锁相状态的检测，禁止分频步骤。因此，在实现了相位锁定之后，从循环中除去添加了减小比较频率的额外的参考分频器（6），从而能够增加环路带宽并减小环路内的分频比。

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