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1. 发明授权

US09077571B2 Adaptive equalizer and/or antenna tuning 有权
标题翻译：自适应均衡器和/或天线调谐
公开(公告)号：US09077571B2
公开(公告)日：2015-07-07
申请号：US13229070
申请日：2011-09-09
申请人： Remco Cornelis Herman van de Beek , Massimo Ciacci
发明人： Remco Cornelis Herman van de Beek , Massimo Ciacci
IPC分类号： H04L25/49 , H03K5/159 , H04L25/02 , H04L25/03 , H04B5/00
CPC分类号： H04L25/0266 , H04B5/0081 , H04L25/03343 , H04L27/368
摘要： Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal.
摘要翻译：为各种应用实现均衡电路和方法。根据一个这样的应用，发射设备使用天线进行无线通信。该设备具有被配置和布置成使用天线和远程设备之间的磁耦合来传输第一无线信号的传输电路，耦合发生在无线介质上。发射设备的接收机电路被配置和布置成接收来自天线的第二无线信号，并且表示通过在无线介质上发生的耦合所修改的第一无线信号。设备的误差电路被配置和布置成通过将第一无线信号与第二无线信号进行比较来产生误差信号。该器件的均衡器电路被配置和布置成通过用补偿误差信号来补偿符号间干扰的编码对第一无线信号进行预编码。

2. 发明申请

US20120269304A1 Symbol Clock Recovery Circuit 有权
标题翻译：符号时钟恢复电路
公开(公告)号：US20120269304A1
公开(公告)日：2012-10-25
申请号：US13417486
申请日：2012-03-12
申请人： Massimo Ciacci , Remco Cornelis Herman Van De Beek , Ghiath Al-kadi
发明人： Massimo Ciacci , Remco Cornelis Herman Van De Beek , Ghiath Al-kadi
IPC分类号： H04L27/06 , H04L7/04
CPC分类号： H04L7/0334 , H04L7/046 , H04L27/22 , H04L2007/047
摘要： A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.
摘要翻译：为使用相干解调的数据通信系统提供符号时钟恢复电路。符号时钟恢复电路包括模数转换器，其包括用于接收从载波信号导出的相干检测的基带模拟信号的第一输入端，用于接收适配符号时钟信号的第二输入端和用于输出数字信号包括具有至少两个符号的前同步码的帧。符号时钟恢复电路还包括一个移相单元，包括用于接收从载波信号导出的符号时钟信号的第一输入端和定时检测器，该定时检测器包括用于从模 - 数转换器接收数字信号的第一输入端和用于向相移单元提供包括关于最佳采样相位的信息的信号的输出。

3. 发明授权

US09172329B2 Harmonic suppression in switching amplifiers 有权
标题翻译：开关放大器谐波抑制
公开(公告)号：US09172329B2
公开(公告)日：2015-10-27
申请号：US13564013
申请日：2012-08-01
申请人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
发明人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
IPC分类号： H03F3/217 , H03F1/32 , H03C5/00 , H03F3/24 , H04L25/02
CPC分类号： H03C5/00 , H03F3/2173 , H03F3/24 , H04L25/0272
摘要： Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.
摘要翻译：考虑到具有两个产生具有引入的谐波的差分输出信号的D类开关放大器的射频（RF）发射机电路中的谐波的可配置抑制。选择的谐波用于确定持续时间。谐波抑制电路修正使用振幅分量和相位分量编码的射频极调制数据信号。修改响应于所确定的持续时间。开关功率放大器放大经修改的极化调制数据信号以产生放大信号。放大的信号包括三个信号电平，高信号电平，中间信号电平和低信号电平。高信号和低信号电平之间的转换时序表示相位分量，并且转换包括持续时间的中间信号电平，从而抑制所选择的谐波。

4. 发明授权

US09038916B2 Smart card with reconfigurable receiver 有权
标题翻译：具有可重构接收器的智能卡
公开(公告)号：US09038916B2
公开(公告)日：2015-05-26
申请号：US13252999
申请日：2011-10-04
申请人： Ghiath Al-Kadi , Massimo Ciacci , Remco Cornelis Herman van de Beek
发明人： Ghiath Al-Kadi , Massimo Ciacci , Remco Cornelis Herman van de Beek
IPC分类号： G06K19/07
CPC分类号： G06K19/0723 , G06K19/07 , H04L1/0053 , H04L1/0075 , H04L1/20 , H04W4/80 , Y02D70/166
摘要： The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.
摘要翻译：本发明提出了一种智能卡，其包括数字信号处理接收器，其可以基于从读取器接收的信号的误差向量大小自动识别智能卡读卡器的类型。数字信号处理接收器能够在运行时重新配置自身，以便根据其正在通信的读取器的类型来最佳化其功耗。此外，本发明提出了一种新的前导码结构，其包括基本部分和可选的附加部分。

5. 发明申请

US20130064271A1 ADAPTIVE EQUALIZER AND/OR ANTENNA TUNING 有权
标题翻译：自适应均衡器和/或天线调谐
公开(公告)号：US20130064271A1
公开(公告)日：2013-03-14
申请号：US13229070
申请日：2011-09-09
申请人： Remco Cornelis Herman van de Beek , Massimo Ciacci
发明人： Remco Cornelis Herman van de Beek , Massimo Ciacci
IPC分类号： H04B1/10 , H04B1/38 , H04L27/01
CPC分类号： H04L25/0266 , H04B5/0081 , H04L25/03343 , H04L27/368
摘要： Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal.
摘要翻译：为各种应用实现均衡电路和方法。根据一个这样的应用，发射设备使用天线进行无线通信。该设备具有被配置和布置成使用天线和远程设备之间的磁耦合来传输第一无线信号的传输电路，耦合发生在无线介质上。发射设备的接收机电路被配置和布置成接收来自天线的第二无线信号，并且表示通过在无线介质上发生的耦合所修改的第一无线信号。设备的误差电路被配置和布置成通过将第一无线信号与第二无线信号进行比较来产生误差信号。该器件的均衡器电路被配置和布置成通过用补偿误差信号来补偿符号间干扰的编码对第一无线信号进行预编码。

6. 发明申请

US20080232213A1 Feedback Control Loop for Bit Detection in an N-Dimensional Data Block 审中-公开
标题翻译：用于N维数据块中位检测的反馈控制回路
公开(公告)号：US20080232213A1
公开(公告)日：2008-09-25
申请号：US10597320
申请日：2005-01-24
申请人： Johannes Wilhelmus Maria Bergmans , Albert Hendrik Jan Immink , Jamal Riani , Willem Marie Julia Marcel Coene , Steven Jena-Marie Lucie Van Beneden , Massimo Ciacci , Ali Nowbakht Irani
发明人： Johannes Wilhelmus Maria Bergmans , Albert Hendrik Jan Immink , Jamal Riani , Willem Marie Julia Marcel Coene , Steven Jena-Marie Lucie Van Beneden , Massimo Ciacci , Ali Nowbakht Irani
IPC分类号： G11B5/58
CPC分类号： G11B20/10046 , G11B20/10 , G11B20/10009 , G11B20/18 , G11B2020/1275 , G11B2020/1288 , G11B2020/1863 , H03M13/41 , H03M13/6331
摘要： On existing DVD and CD players a control loop is required for the adaptation and timing recovery. For Two-Dimensional Optical Storage such a control loop has drawbacks because PRML detection in the form of a stripe-wise Viterbi detector is used. Such a detector introduces an increasing detection delay when going from the outer rows towards the center of the broad spiral. A feedback loop is arranged to determining an error signal from a first area of the data block where the first area is that area where the error signal can be determined within the shortest period of time. This reduces the duration of the detection step and thus increases the stability of the control loop.
摘要翻译：在现有的DVD和CD播放机上，适配和定时恢复需要一个控制环路。对于二维光学存储，这样的控制回路具有缺点，因为使用了带状维特比检测器形式的PRML检测。这种检测器在从外排朝向宽螺旋的中心时引入增加的检测延迟。反馈环路被布置成从数据块的第一区域确定误差信号，其中第一区域是可以在最短时间内确定误差信号的区域。这减少了检测步骤的持续时间，从而增加了控制回路的稳定性。

7. 发明授权

US08781051B2 Symbol clock recovery circuit 有权
标题翻译：符号时钟恢复电路
公开(公告)号：US08781051B2
公开(公告)日：2014-07-15
申请号：US13417486
申请日：2012-03-12
申请人： Massimo Ciacci , Remco Cornelis Herman van de Beek , Ghiath Al-kadi
发明人： Massimo Ciacci , Remco Cornelis Herman van de Beek , Ghiath Al-kadi
IPC分类号： H04L7/00
CPC分类号： H04L7/0334 , H04L7/046 , H04L27/22 , H04L2007/047
摘要： A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.
摘要翻译：为使用相干解调的数据通信系统提供符号时钟恢复电路。符号时钟恢复电路包括模数转换器，其包括用于接收从载波信号导出的相干检测的基带模拟信号的第一输入端，用于接收适配符号时钟信号的第二输入端和用于输出数字信号包括具有至少两个符号的前同步码的帧。符号时钟恢复电路还包括一个移相单元，包括用于接收从载波信号导出的符号时钟信号的第一输入端和定时检测器，该定时检测器包括用于从模 - 数转换器接收数字信号的第一输入端和用于向相移单元提供包括关于最佳采样相位的信息的信号的输出。

8. 发明申请

US20140038534A1 HARMONIC SUPPRESSION IN SWITCHING AMPLIFIERS 有权
标题翻译：谐波抑制在开关放大器
公开(公告)号：US20140038534A1
公开(公告)日：2014-02-06
申请号：US13564013
申请日：2012-08-01
申请人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
发明人： Massimo Ciacci , Jos Verlinden , Remco van de Beek
IPC分类号： H03C1/52
CPC分类号： H03C5/00 , H03F3/2173 , H03F3/24 , H04L25/0272
摘要： Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.
摘要翻译：考虑到具有两个产生具有引入的谐波的差分输出信号的D类开关放大器的射频（RF）发射机电路中的谐波的可配置抑制。选择的谐波用于确定持续时间。谐波抑制电路修正使用振幅分量和相位分量编码的射频极调制数据信号。修改响应于所确定的持续时间。开关功率放大器放大经修改的极化调制数据信号以产生放大信号。放大的信号包括三个信号电平，高信号电平，中间信号电平和低信号电平。高信号和低信号电平之间的转换时序表示相位分量，并且转换包括持续时间的中间信号电平，从而抑制所选择的谐波。

9. 发明授权

US08378710B1 Secure device anti-tampering circuit 有权
标题翻译：安全装置防篡改电路
公开(公告)号：US08378710B1
公开(公告)日：2013-02-19
申请号：US13237122
申请日：2011-09-20
申请人： Ghiath Al-Kadi , Jan Hoogerbrugge , Massimo Ciacci
发明人： Ghiath Al-Kadi , Jan Hoogerbrugge , Massimo Ciacci
IPC分类号： H03K19/003
CPC分类号： G06K19/07372
摘要： Various embodiments relate to an anti-tampering circuit for a secure device including: a signal delay detector; a clock delay detector; a clock duty cycle detector; and a protection unit that receives an error indication from the signal delay detector, clock delay detector, and the clock duty cycle detector, wherein the protection unit indicates tampering to a secure device upon receiving the error indication.
摘要翻译：各种实施例涉及一种用于安全装置的防篡改电路，包括：信号延迟检测器; 时钟延迟检测器; 时钟占空比检测器; 以及保护单元，其从所述信号延迟检测器，时钟延迟检测器和所述时钟占空比检测器接收错误指示，其中所述保护单元在接收到所述错误指示时指示对安全设备的篡改。

10. 发明申请

US20120080529A1 SMART CARD 有权
标题翻译：智能卡
公开(公告)号：US20120080529A1
公开(公告)日：2012-04-05
申请号：US13252999
申请日：2011-10-04
申请人： Ghiath Al-Kadi , Massimo Ciacci , Remco Cornelis Herman van de Beek
发明人： Ghiath Al-Kadi , Massimo Ciacci , Remco Cornelis Herman van de Beek
IPC分类号： G06K19/073
CPC分类号： G06K19/0723 , G06K19/07 , H04L1/0053 , H04L1/0075 , H04L1/20 , H04W4/80 , Y02D70/166
摘要： The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.
摘要翻译：本发明提出了一种智能卡，其包括数字信号处理接收器，其可以基于从读取器接收的信号的误差向量大小自动识别智能卡读卡器的类型。数字信号处理接收器能够在运行时重新配置自身，以便根据其正在通信的读取器的类型来最佳化其功耗。此外，本发明提出了一种新的前导码结构，其包括基本部分和可选的附加部分。

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