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1. 发明授权

US5483283A Three level high speed clock driver for an image sensor 失效
标题翻译：用于图像传感器的三级高速时钟驱动器
公开(公告)号：US5483283A
公开(公告)日：1996-01-09
申请号：US247725
申请日：1994-05-23
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H04N5/335 , H04N5/376 , H03K4/24
CPC分类号： H04N5/335
摘要： A high speed clock driver circuit for use with an area image sensor which has two horizontal shift registers is disclosed. Circuitry is provided which is responsive to the third level of one of the horizontal high speed clock driver signal and the vertical transfer signals for enabling the transfer, in parallel, of pixels from the first register into the second horizontal shift register.
摘要翻译：公开了一种与具有两个水平移位寄存器的区域图像传感器一起使用的高速时钟驱动电路。提供了电路，其响应于水平高速时钟驱动器信号和垂直传输信号中的一个的第三电平，用于使得能够并行地将从第一寄存器到第二水平移位寄存器的像素传送。

2. 发明授权

US4866299A Remotely driving a CCD 失效
标题翻译：远程驱动CCD
公开(公告)号：US4866299A
公开(公告)日：1989-09-12
申请号：US227046
申请日：1988-08-01
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H03K17/0814 , H03K17/10
CPC分类号： H03K17/08146 , H03K17/10
摘要： A clock driver apparatus for remotely driving a CCD capacitive load includes a coaxial cable, a reactance load and a driver circuit having a resistor and diode connected in parallel at the output of the circuit to provide short circuit protection for the switching transistors of the driver circuit.
摘要翻译：用于远程驱动CCD电容性负载的时钟驱动器装置包括同轴电缆，电抗负载和具有在电路输出处并联连接的电阻器和二极管的驱动器电路，以为驱动器电路的开关晶体管提供短路保护。

3. 发明授权

US5483155A Test system and method for dynamic testing of a plurality of packaged same-type charge coupled device image sensors 失效
标题翻译：用于多个封装的相同类型电荷耦合器件图像传感器的动态测试的测试系统和方法
公开(公告)号：US5483155A
公开(公告)日：1996-01-09
申请号：US306348
申请日：1994-09-15
申请人： Ram Kannegundla , Russell J. Taras
发明人： Ram Kannegundla , Russell J. Taras
IPC分类号： G11C29/50 , H01L27/148 , H04N17/00 , G01R31/28
CPC分类号： H04N17/002 , G11C29/50 , H01L27/148
摘要： A test system is provided for the dynamic testing at the same time of a plurality of packaged charge coupled device (CCD) image sensors in which the plurality of image sensors of the same sensor type can be tested under conditions including selectable signal levels of bias control signals and selected signal levels and pulse durations of clocked control signals appropriate to the type of CCD image sensor of the plurality of sensors under test. The test system provides selectably level-adjusted control signals, selector switch means for generating selectable clock signals having the level-adjusted signal levels, and a clock driver for amplifying the clocked control signals. The amplified control signals are directed to a common input terminal of an isolation network assembly, each of separate output terminals thereof connected to a corresponding input terminal of each one of the CCD image sensors to be tested. The test system is designed such that a sole remaining functioning CCD image sensor of the plurality of sensors can still be dynamically tested while all others of the plurality of CCD image sensors have experienced a catastrophic short-circuit condition at the corresponding clocked-signal input terminal.
摘要翻译：提供了用于在多个封装的电荷耦合器件（CCD）图像传感器的同时的动态测试的测试系统，其中可以在包括偏置控制的可选信号电平的条件下测试相同传感器类型的多个图像传感器时钟控制信号的信号和选择的信号电平和脉冲持续时间，其适合于被测试的多个传感器的CCD图像传感器的类型。测试系统提供可选择的电平调节的控制信号，用于产生具有电平调整的信号电平的可选择时钟信号的选择器开关装置，以及用于放大时钟控制信号的时钟驱动器。放大的控制信号被引导到隔离网络组件的公共输入端，其每个独立的输出端连接到要测试的每个CCD图像传感器的相应输入端。测试系统被设计成使得多个传感器中的唯一剩余的功能的CCD图像传感器仍然可以被动态地测试，而所有这些多个CCD图像传感器中的所有其它CCD图像传感器在相应的时钟信号输入端子处经历了灾难性的短路状态。

4. 发明授权

US4761565A CCD clock driver circuit 失效
标题翻译： CCD时钟驱动电路
公开(公告)号：US4761565A
公开(公告)日：1988-08-02
申请号：US67749
申请日：1987-06-29
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： G11C19/28 , H03K17/0814 , H03K17/12
CPC分类号： H03K17/08146 , G11C19/285 , H03K17/08142 , H03K17/12 , H03K17/122
摘要： A high-speed CCD clock driver circuit is obtained by coupling a plurality of driver circuits in parallel, with each driver circuit including a short circuit protection circuit consisting of the parallel connection of a resistor and a diode. In a further embodiment, a plurality of pre-driver circuits are connected in parallel to provide drive to the parallel-connected driver circuits.
摘要翻译：通过并联多个驱动电路来获得高速CCD时钟驱动器电路，每个驱动电路包括由电阻器和二极管的并联连接构成的短路保护电路。在另一实施例中，多个预驱动器电路并联连接以向并联连接的驱动器电路提供驱动。

5. 发明授权

US06184928B2 Method and apparatus for split shift register addressing 失效
标题翻译：分离移位寄存器寻址的方法和装置
公开(公告)号：US06184928B2
公开(公告)日：2001-02-06
申请号：US08846392
申请日：1997-04-30
申请人： Ram Kannegundla , Timothy J. Kenney, Sr. , Robert M. Guidash
发明人： Ram Kannegundla , Timothy J. Kenney, Sr. , Robert M. Guidash
IPC分类号： H04N314
CPC分类号： G11C7/1018 , G11C8/04
摘要： An addressing circuit designed for implementation within the device being addressed that uses less silicon space by selecting the desired address with shift register outputs. A fast shift register is coupled to a slow shift register by a combinatorial circuit having inputs from the fast shift register and the slow shift register to providing the selected address. A timing circuit is electrically coupled to each the fast shift register and the slow shift register. A mode select circuit that is operatively coupled to at least one of either the fast shift register or the slow shift register. The mode select circuit comprises a Boolean logic circuit that is operatively coupled to at least one of either the slow shift register or the fast shift register, the Boolean logic circuit having at least one logical input that determine a first portion of at least one of the shift registers to be used and a second portion of at least one of the shift registers to be discarded.
摘要翻译：设计用于在被寻址的器件中实现的寻址电路，其通过使用移位寄存器输出选择所需的地址而使用较少的硅空间。快速移位寄存器通过具有来自快速移位寄存器和慢移位寄存器的输入的组合电路耦合到慢速移位寄存器以提供所选择的地址。定时电路电耦合到每个快速移位寄存器和慢速移位寄存器。模式选择电路，其可操作地耦合到快速移位寄存器或慢移位寄存器中的至少一个。模式选择电路包括可操作地耦合到慢速移位寄存器或快速移位寄存器中的至少一个的布尔逻辑电路，布尔逻辑电路具有至少一个逻辑输入，其确定至少一个的第一部分要使用的移位寄存器和待丢弃的至少一个移位寄存器的第二部分。

6. 发明授权

US5489945A Timing logic system and method for selectably controlling a high resolution charge coupled device image sensor of the type having two line pixel registers to provide a high resolution mode and alternatively a television resolution mode of picture imaging 失效
标题翻译：用于可选择地控制具有两个线像素寄存器的类型的高分辨率电荷耦合器件图像传感器的时序逻辑系统和方法，以提供高分辨率模式，或者可选地，电视分辨率模式的图像成像
公开(公告)号：US5489945A
公开(公告)日：1996-02-06
申请号：US305244
申请日：1994-09-13
申请人： Ram Kannegundla , Win-Chyi Chang
发明人： Ram Kannegundla , Win-Chyi Chang
IPC分类号： H04N5/343 , H04N5/372 , H04N5/376 , H04N5/06 , H04N5/067
CPC分类号： H04N3/1575 , H04N3/155
摘要： A timing logic system which includes a generic television-standard timing generator selectably provides precisely timed horizontal and vertical control signals for controlling the operation of a high resolution charge coupled device (CCD) image sensor of the type having two line pixel registers in a high resolution mode of picture imaging. Alternatively, the timing logic system selectably provides precisely timed horizontal and vertical control signals, and a precisely timed display field control signal applied to a switch mechanism, for controlling the operation of the high resolution CCD image sensor in a television resolution mode of picture imaging in accordance with a television standard, for example, the NTSC standard. The timing logic system also provides sync and control signals to a television-standard display in the television mode of operation. In both the high resolution mode and the television mode of operation, the timing logic system provides the respective horizontal and vertical control signals to the CCD image sensor so that both line pixel registers are operative.
摘要翻译：包括通用电视标准定时发生器的定时逻辑系统可选地提供精确定时的水平和垂直控制信号，用于控制具有高分辨率的两个线像素寄存器的类型的高分辨率电荷耦合器件（CCD）图像传感器的操作图像成像模式。或者，定时逻辑系统可选地提供精确定时的水平和垂直控制信号，以及施加到开关机构的精确定时的显示场控制信号，用于在电视分辨率图像成像模式中控制高分辨率CCD图像传感器的操作按照电视标准，例如NTSC标准。定时逻辑系统还在电视操作模式中向电视标准显示器提供同步和控制信号。在高分辨率模式和电视操作模式中，定时逻辑系统向CCD图像传感器提供相应的水平和垂直控制信号，使得两个线像素寄存器都可操作。

7. 发明授权

US5523788A Image processor with input buffering to multiple digital signal processors 失效
标题翻译：具有输入缓冲的多个数字信号处理器的图像处理器
公开(公告)号：US5523788A
公开(公告)日：1996-06-04
申请号：US313632
申请日：1994-09-27
申请人： Ram Kannegundla , Lionel J. D'Luna , Yung-Rai Lee
发明人： Ram Kannegundla , Lionel J. D'Luna , Yung-Rai Lee
IPC分类号： G09G5/393 , H04N5/335 , H04N5/343 , H04N5/372 , H04N5/378
CPC分类号： H04N5/335 , G09G5/393
摘要： A system architecture is provided that includes an image sensor unit operable in a single channel mode and a dual channel mode. The image sensor unit includes an electronic image sensor comprising a row and column array of pixel elements, wherein the rows of the array having a line length of N pixels. First and second digital signal processing units for processing image data generated by the image sensor unit into color component image data are provided, wherein each of said first and second digital signal processing units has a line length processing capacity less than N pixels. An input buffer, coupled between outputs of the image sensor unit and inputs to the digital signal processing units, simultaneously receives two lines of image data from the image sensor unit in the dual channel mode of operation, and sequentially supplies a first portion of each of the simultaneously received image lines to the first digital signal processing unit and a second portion of each of the simultaneously received image lines to the second digital signal processing unit. An output buffer, coupled to the output of the first and second digital signal processing units, combines the color component image data generated by the first and second digital signal processing units into color component image lines of length N pixels. A control unit controls the operation of the image sensor unit, the input buffer, the first and second digital signal processing units, and the output buffer. A frame store receives and stores the color component image lines generated by the output buffer, and a monitor displays the image lines at a frame rate that is about twice the operating frame rate of the image sensor unit.
摘要翻译：提供了一种系统架构，其包括可在单通道模式和双通道模式下操作的图像传感器单元。图像传感器单元包括电子图像传感器，其包括像素元件的行和列阵列，其中阵列的行具有N个像素的线长度。提供了用于将由图像传感器单元生成的图像数据处理为彩色分量图像数据的第一和第二数字信号处理单元，其中所述第一和第二数字信号处理单元中的每一个具有小于N个像素的行长处理能力。耦合到图像传感器单元的输出和数字信号处理单元的输入之间的输入缓冲器在双通道操作模式中同时从图像传感器单元接收两行图像数据，并且顺序地将第一部分的同时接收到的图像行到第一数字信号处理单元和每个同时接收的图像行的第二部分到第二数字信号处理单元。耦合到第一和第二数字信号处理单元的输出的输出缓冲器将由第一和第二数字信号处理单元生成的颜色分量图像数据组合成长度为N个像素的颜色分量图像行。控制单元控制图像传感器单元，输入缓冲器，第一和第二数字信号处理单元以及输出缓冲器的操作。帧存储器接收并存储由输出缓冲器生成的颜色分量图像线，并且监视器以大约是图像传感器单元的操作帧速率的两倍的帧速率显示图像行。

8. 发明授权

US5396290A Apparatus and method for controlling a high resolution charge coupled device image sensor to provide alternative modes of picture imaging 失效
标题翻译：用于控制高分辨率电荷耦合器件图像传感器以提供替代图像成像模式的装置和方法
公开(公告)号：US5396290A
公开(公告)日：1995-03-07
申请号：US33908
申请日：1993-03-19
申请人： Ram Kannegundla , Win-Chyi Chang
发明人： Ram Kannegundla , Win-Chyi Chang
IPC分类号： H04N5/335 , H04N5/343 , H04N5/372 , H04N3/15
CPC分类号： H04N3/155 , H04N5/335
摘要： Apparatus and method for controlling a high resolution charge coupled device (CCD) image sensor operate in accordance with a television standard to provide horizontal, vertical, and other CCD control signals to obtain a purely sequential high resolution mode of operation on the one hand. Alternatively, there is a modified mode of operation which provides interlaced even and odd groups of video signals to be viewed directly on a television viewfinder display. The apparatus includes a frequency generator, a standard timing generator, a pixel clock generator, and a small number of additional timers and logic units which are driven by signals from the generators to selectably generate the vertical, horizontal, and other CCD control signals for the alternate modes of operation. The method includes generating a plurality of precisely timed pulses referenced to television standard synchronizing and control signals, and logically combining these pulses and standard signals to generate vertical, horizontal, and other CCD control signals.
摘要翻译：一方面，用于控制高分辨率电荷耦合器件（CCD）图像传感器的装置和方法根据电视标准进行操作，以提供水平，垂直和其它CCD控制信号，从而一方面获得纯序列高分辨率操作模式。或者，存在修改的操作模式，其提供在电视取景器显示器上直接观看的隔行偶数和奇数组视频信号。该装置包括频率发生器，标准定时发生器，像素时钟发生器，以及由来自发生器的信号驱动的少量额外的定时器和逻辑单元，以可选地生成垂直，水平和其它CCD控制信号替代操作模式。该方法包括产生参考电视标准同步和控制信号的多个精确定时脉冲，以及逻辑地组合这些脉冲和标准信号以产生垂直，水平和其它CCD控制信号。

9. 发明授权

US5258659A Timed delayed digital signal producing circuit 失效
标题翻译：定时延迟数字信号产生电路
公开(公告)号：US5258659A
公开(公告)日：1993-11-02
申请号：US922410
申请日：1992-07-31
申请人： Ram Kannegundla
发明人： Ram Kannegundla
IPC分类号： H03K5/13 , H03K5/12 , H03K5/01
CPC分类号： H03K5/13
摘要： A time delayed digital circuit includes two inverters used in charging and disclosure a capacitor to produce a precisely delayed output digital signal.
摘要翻译：时间延迟数字电路包括两个逆变器，用于对电容器进行充电和公开以产生精确延迟的输出数字信号。

10. 发明授权

US5210614A Display interface for high resolution CCD video sensor 失效
标题翻译：高分辨率CCD视频传感器的显示界面
公开(公告)号：US5210614A
公开(公告)日：1993-05-11
申请号：US705848
申请日：1991-05-28
申请人： Ram Kannegundla , Win-Chyi Chang
发明人： Ram Kannegundla , Win-Chyi Chang
IPC分类号： H04N5/335
CPC分类号： H04N5/335
摘要： A low cost system for efficiently doubling the data readout rate from a high resolution CCD video sensor having two line outputs includes a pair of analog to digital converters, a separate pair of first-in first-out line stores for each of the analog to digital converters, and a digital to analog converter. Successive lines from the video sensor are fed into alternate ones of the analog to digital converters in sequence at the normal pixel clock frequency used with other than high resolution sensors. The contents of successive lines in each of the analog to digital converters are written into alternate ones of its respective pair of line stores in sequence. The contents of successive lines from all of the line stores are fed into the digital to analog converter. Finally, analog data is read out of the digital to analog converter to the single analog input of a high resolution video monitor at twice the pixel clock frequency. The entire system is made up of off-the-shelf components which are compact and relatively inexpensive.
摘要翻译：一种低成本系统，用于从具有两个线路输出的高分辨率CCD视频传感器有效地将数据读出速率加倍，包括一对模数转换器，每对模数转换器分开的一对先进先出存储线转换器和数模转换器。来自视频传感器的连续线在与高分辨率传感器不同的正常像素时钟频率下依次馈送到模数转换器中的替代线。每个模数转换器中的连续行的内容被顺序地写入其相应的一对行存储库中的替代数据。来自所有线路存储器的连续行的内容被馈送到数模转换器。最后，模拟数据从数模转换器读取到高分辨率视频监视器的单模拟输入，以两倍于像素时钟频率。整个系统由紧凑且相对便宜的现成组件组成。

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