专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08415986B2 Voltage-mode driver with pre-emphasis 有权
标题翻译：电压模式驱动器，预加重
公开(公告)号：US08415986B2
公开(公告)日：2013-04-09
申请号：US12979337
申请日：2010-12-28
申请人： Sumantra Seth , Rajavelu Thinakaran
发明人： Sumantra Seth , Rajavelu Thinakaran
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/03343
摘要： A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.
摘要翻译：支持预加重的电压模式驱动电路包括多个电阻，多个晶体管用作开关。操作晶体管的控制信号表示到驱动器电路的输入信号的逻辑电平。为了产生预加重输出，晶体管被操作以在驱动器的输出端子和对应的恒定参考电位之间连接电阻器的并联布置。为了在稳态下产生输出，晶体管被操作以连接驱动器的输出端上的一些电阻，从而降低输出电压。通过适当选择电阻器的电阻值来获得驱动器的期望的输出阻抗和期望的预加重电平。在稳态下，司机的电流消耗比预加重模式要小。

2. 发明申请

US20120161816A1 VOLTAGE-MODE DRIVER WITH PRE-EMPHASIS 有权
标题翻译：电压模式驱动器与前瞻性
公开(公告)号：US20120161816A1
公开(公告)日：2012-06-28
申请号：US12979337
申请日：2010-12-28
申请人： Sumantra Seth , Rajavelu Thinakaran
发明人： Sumantra Seth , Rajavelu Thinakaran
IPC分类号： H03K3/00
CPC分类号： H03K19/018521 , H04L25/0272 , H04L25/0278 , H04L25/028 , H04L25/03343
摘要： A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.
摘要翻译：支持预加重的电压模式驱动电路包括多个电阻，多个晶体管用作开关。操作晶体管的控制信号表示到驱动器电路的输入信号的逻辑电平。为了产生预加重输出，晶体管被操作以在驱动器的输出端子和对应的恒定参考电位之间连接电阻器的并联布置。为了在稳态下产生输出，晶体管被操作以连接驱动器的输出端上的一些电阻，从而降低输出电压。通过适当选择电阻器的电阻值来获得驱动器的期望的输出阻抗和期望的预加重电平。在稳态下，司机的电流消耗比预加重模式要小。

3. 发明授权

US07852110B2 Controlling the slew-rate of an output buffer 有权
标题翻译：控制输出缓冲区的转换速率
公开(公告)号：US07852110B2
公开(公告)日：2010-12-14
申请号：US12467311
申请日：2009-05-18
申请人： Sumantra Seth , Sneha Teresa Thomas
发明人： Sumantra Seth , Sneha Teresa Thomas
IPC分类号： H03K19/003
CPC分类号： H03K5/04 , H03K19/00361
摘要： An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer.
摘要翻译：根据本发明的一个方面提供的输出缓冲器被设计成产生一个输出信号，该转换速率基本上与包含在其中的晶体管的阈值电压无关。根据本发明的另一方面提供的输出缓冲器根据输出缓冲器的输出节点处的负载电容的大小提供具有不同转换速率的输出信号。

4. 发明授权

US07471111B2 Slew-rate controlled pad driver in digital CMOS process using parasitic device cap 有权
标题翻译：使用寄生器件帽的数字CMOS工艺中的压摆率控制焊盘驱动器
公开(公告)号：US07471111B2
公开(公告)日：2008-12-30
申请号：US11696247
申请日：2007-04-04
申请人： Sumantra Seth , Ankush Goel
发明人： Sumantra Seth , Ankush Goel
IPC分类号： H03K19/094
CPC分类号： H03K19/01721
摘要： A slew-rate controlled driver circuit in an integrated circuit fabricated in a low voltage CMOS process, having an input node and an output node. A PMOS pull-up transistor is provided, having a source connected to one side of a power supply, having a gate, and having a drain connected to the output node. The PMOS transistor also has a parasitic capacitance between its gate and drain, having a value that may vary from one integrated circuit to the next from process variations and in response to varying circuit conditions. A current source generates a current having a level corresponding to the value of the parasitic capacitance, and to provide that current to the gate of the PMOS transistor. A level shifter receives an input signal having a voltage varying in a first range provides as output signal to the gate of the PMOS transistor shifted to a level suitable for the PMOS transistor. An NMOS pull-down transistor is also provided, connected to the other side of the power supply, with a similar and corresponding current source and level shifter as has the PMOS transistor.
摘要翻译：在低电压CMOS工艺中制造的集成电路中的转换速率控制的驱动器电路，具有输入节点和输出节点。提供PMOS上拉晶体管，其源极连接到电源的一侧，具有栅极，并且具有连接到输出节点的漏极。 PMOS晶体管在其栅极和漏极之间也具有寄生电容，具有可以根据工艺变化和响应于变化的电路条件从一个集成电路到下一个变化的值。电流源产生具有与寄生电容的值相对应的电平的电流，并将该电流提供给PMOS晶体管的栅极。电平移位器接收具有在第一范围内变化的电压的输入信号作为输出信号提供给PMOS晶体管的栅极，该PMOS晶体管的栅极转换到适合于PMOS晶体管的电平。还提供了NMOS电源和与PMOS晶体管相同的电流移位器连接到电源的另一侧的NMOS下拉晶体管。

5. 发明授权

US08649136B2 Thin-oxide current clamp 有权
标题翻译：薄氧化物电流钳
公开(公告)号：US08649136B2
公开(公告)日：2014-02-11
申请号：US13226498
申请日：2011-09-07
申请人： Sumantra Seth , Jayesh Wadekar
发明人： Sumantra Seth , Jayesh Wadekar
IPC分类号： H02H9/00
CPC分类号： H02H9/041
摘要： A thin-oxide current clamp includes a clamp transistor in current-conducting relation between a voltage-sensitive circuit and a common return of a power supply, the clamp transistor responsive to a sense output signal to provide a low-resistance current flow path from the voltage-sensitive circuit to the common return and thereby clamp a voltage in the voltage-sensitive circuit. The thin-oxide current clamp also includes a current source and a reference current mirror, the reference current mirror providing a reference current. Further, the thin-oxide current clamp includes a sense current mirror providing a sense current. Further, the thin-oxide current clamp also includes an output transistor that receives the sense current and provides a current flow to a gate of the clamp transistors if the sense current exceeds the reference current.
摘要翻译：薄氧化物电流钳包括在电压敏感电路和电源的公共返回之间的导通关系中的钳位晶体管，所述钳位晶体管响应于感测输出信号以提供来自所述电源的低电阻电流流动路径电压敏感电路到公共返回，从而在电压敏感电路中钳位电压。薄氧化物电流钳还包括电流源和参考电流镜，参考电流镜提供参考电流。此外，薄氧化物电流钳包括提供感测电流的感测电流镜。此外，薄氧化物电流钳还包括输出晶体管，其接收感测电流，并且如果感测电流超过参考电流，则向钳位晶体管的栅极提供电流。

6. 发明授权

US07830183B2 Comparator with reduced power consumption 有权
标题翻译：比较器功耗降低
公开(公告)号：US07830183B2
公开(公告)日：2010-11-09
申请号：US12333299
申请日：2008-12-11
申请人： Sumantra Seth , Abhijith Arakali
发明人： Sumantra Seth , Abhijith Arakali
IPC分类号： H03B1/00
CPC分类号： H03K5/082 , H03K3/011 , H03K3/3565
摘要： A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.
摘要翻译：比较器部件具有比较电路和偏置发生器电路，偏置发生器电路也具有与比较电路中包含的相同配置的相同数量的晶体管，以产生比较结果，该比较结果基于由偏置发生电路。接收偏置信号的比较电路的晶体管以电流反射镜配置连接到偏置发生器电路中的相应晶体管。相同的偏置电路可以由相应的比较器部件的许多比较电路共享。可以扩展这些特性以提供迟滞。

7. 发明申请

US20090289669A1 CONTROLLING THE SLEW-RATE OF AN OUTPUT BUFFER 有权
标题翻译：控制输出缓冲器的频率
公开(公告)号：US20090289669A1
公开(公告)日：2009-11-26
申请号：US12467311
申请日：2009-05-18
申请人： Sumantra Seth , Sneha Teresa Thomas
发明人： Sumantra Seth , Sneha Teresa Thomas
IPC分类号： H03K3/00
CPC分类号： H03K5/04 , H03K19/00361
摘要： An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer.
摘要翻译：根据本发明的一个方面提供的输出缓冲器被设计成产生一个输出信号，该转换速率基本上与包含在其中的晶体管的阈值电压无关。根据本发明的另一方面提供的输出缓冲器根据输出缓冲器的输出节点处的负载电容的大小提供具有不同转换速率的输出信号。

8. 发明授权

US08138806B2 Driver circuit for high voltage differential signaling 有权
标题翻译：用于高压差分信号的驱动电路
公开(公告)号：US08138806B2
公开(公告)日：2012-03-20
申请号：US12690115
申请日：2010-01-20
申请人： Jayesh Gangaprasad Wadekar , Sumantra Seth , Kartik Reddy
发明人： Jayesh Gangaprasad Wadekar , Sumantra Seth , Kartik Reddy
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H04L25/0272
摘要： Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first output in response to an input. The circuit also includes a first current element coupled to the first positive driver to enable generation of a current. Further, the circuit includes a first negative driver coupled to the first current element, and responsive to the input and the current, due to the first current element, to generate a first negative transition, at a second output, at a rate similar to that of the first positive transition.
摘要翻译：用于高压差分信号的驱动电路。该电路包括第一正驱动器，其响应于输入在第一输出端产生第一正跃迁。该电路还包括耦合到第一正驱动器的第一电流元件以实现电流的产生。此外，电路包括耦合到第一电流元件的第一负驱动器，并且响应于由第一电流元件引起的输入和电流，在第二输出处产生第一负转变，速率类似于的第一个积极的过渡。

9. 发明申请

US20100148854A1 COMPARATOR WITH REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的比较器
公开(公告)号：US20100148854A1
公开(公告)日：2010-06-17
申请号：US12333299
申请日：2008-12-11
申请人： Sumantra Seth , Abhijith Arakali
发明人： Sumantra Seth , Abhijith Arakali
IPC分类号： G05F1/10
CPC分类号： H03K5/082 , H03K3/011 , H03K3/3565
摘要： A comparator component having a comparison circuit and bias generator circuit, with the bias generator circuit also having a same number of transistors connected in an identical configuration, as those contained in the comparison circuit to generate a comparison result based on the bias signal generated by the bias generator circuit. A transistor of the comparison circuit receiving the bias signal is connected to a corresponding transistor in the bias generator circuit, in a current mirror configuration. The same bias circuit may be shared by many comparison circuits of corresponding comparator components. The features can be extended to provide hysteresis.
摘要翻译：比较器部件具有比较电路和偏置发生器电路，偏置发生器电路也具有与比较电路中包含的相同配置的相同数量的晶体管，以产生比较结果，该比较结果基于由偏置发生电路。接收偏置信号的比较电路的晶体管以电流反射镜配置连接到偏置发生器电路中的相应晶体管。相同的偏置电路可以由相应的比较器部件的许多比较电路共享。可以扩展这些特性以提供迟滞。

10. 发明授权

US07522003B2 Constant margin CMOS biasing circuit 有权
标题翻译：恒定裕量CMOS偏置电路
公开(公告)号：US07522003B2
公开(公告)日：2009-04-21
申请号：US11616043
申请日：2006-12-26
申请人： Sumantra Seth , Somasunder Kattepura Sreenath
发明人： Sumantra Seth , Somasunder Kattepura Sreenath
IPC分类号： H03F3/04
CPC分类号： H03F1/301 , G05F3/205 , H03F1/223 , H03F2200/453 , H03F2200/78 , H03F2200/91
摘要： A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element. The amplifier having a first input terminal to couple to receive the primary voltage from the primary biasing circuit, a second input terminal to couple to receive the replica voltage from the replica biasing circuit, and an output terminal to couple to the primary biasing circuit to adaptively adjust a current through the primary biasing circuit according to the received voltages. Further, a current mirror circuit is provided having the biasing circuit.
摘要翻译：提出一种偏置电路。偏置电路包括初级偏置电路，复制电路和放大器。主电路提供偏置电压和初级电压。偏置电压是偏置电路的输出。复制偏置电路提供复制电压。复制偏置电路包括第一电阻元件，所述第一电阻元件具有电阻特性; 第一电流源，所述第一电流源具有用于产生作为第一电阻元件的函数的电流的第一电阻元件; 耦合以接收第一电流源以在第一节点处产生复制电压的第一节点; 第二个电流源; 耦合以接收第二电流源的第二节点和耦合在第一和第二节点之间的第二电阻元件，所述第二电阻元件具有与第一电阻元件基本相似的电阻特性。所述放大器具有第一输入端子以耦合以从主偏置电路接收初级电压，第二输入端子耦合以从复制偏置电路接收复制电压，以及输出端子以自适应地耦合到主偏置电路根据接收的电压调整通过初级偏置电路的电流。此外，提供具有偏置电路的电流镜电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式