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1. 发明授权

US5838299A RGB/YUV video convolution system 失效
标题翻译： RGB / YUV视频卷积系统
公开(公告)号：US5838299A
公开(公告)日：1998-11-17
申请号：US433096
申请日：1995-05-03
申请人： R. Steven Smith , Laurence A. Thompson
发明人： R. Steven Smith , Laurence A. Thompson
IPC分类号： H04N9/00 , G09G5/02 , G09G5/395 , H04N9/64 , H04N9/69 , G09G5/36 , H04N9/77
CPC分类号： G09G5/395 , G09G2310/0224
摘要： An apparatus and a method are provided for smoothing out high frequency information in an interlaced computer generated display. A computer generated RGB signal is converted into a YUV signal, which is separated into its Y, U, and V components. The Y component is convolved by averaging a current scan line with a line above and a line below the current scan line so that black lines are lightened and white lines are darkened, thus avoiding flicker. Since convolution is only performed on the Y part of the YUV signal, only two line buffers, each having a width equal to the number of bits in the Y component only, are required.
摘要翻译：提供了一种在隔行计算机生成的显示中平滑高频信息的装置和方法。计算机生成的RGB信号被转换成YUV信号，其被分成其Y，U和V分量。通过对当前扫描线与当前扫描线以下的线进行平均，将Y分量进行卷积，使黑线变亮，白线变暗，避免闪烁。由于仅在YUV信号的Y部分执行卷积，因此仅需要两个线缓冲器，每个线缓冲器的宽度等于仅Y分量中的位数。

2. 发明授权

US5721949A Disk controller having sequential digital logic in a state machine for transferring data between DMA device and disk drive with minimal assistance of the CPU 失效
标题翻译：磁盘控制器在状态机中具有顺序数字逻辑，用于在CPU的最少辅助下在DMA设备和磁盘驱动器之间传送数据
公开(公告)号：US5721949A
公开(公告)日：1998-02-24
申请号：US863681
申请日：1997-05-27
申请人： R. Steven Smith , Matthew R. Nelson
发明人： R. Steven Smith , Matthew R. Nelson
IPC分类号： G06F3/06 , G11B19/02 , G11B20/12 , G06F15/40
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0676 , G11B19/02 , G11B20/1252
摘要： A method for transferring data between a host computer and peripheral storage including the steps of: (a) receiving data from the host; (b) determining if an escape command is present in the data; (c) writing the data to the a peripheral storage medium if a escape command is not present in the data; and (d) performing as least one command relative to the peripheral storage if a escape command is present in the data. Also disclosed is a method for controlling a disk drive unit including the steps of: (a) determining on a host computer a current action to be performed with a disk drive unit; (b) formatting a track of a disk engaged with a disk drive unit based upon output data provided by the host computer if the current action is a formatting action; (c) writing a sector on the disk based upon the output data provided by the host computer if the current action is a writing action; and (d) reading a sector of the disk and transferring input information to the host computer if the action is a reading action. Escape codes are used to distinguish "normal" data from "special" data. A disk drive controller of the present invention includes digital logic responsive to a data bus of the host computer and operative to develop a datatype bus based on the data bus, where the datatype bus is operative to specify one of a plurality of data types, and a converter responsive to the data bus and the datatype bus and operative to provide serial data to a disk drive unit mechanism.
摘要翻译：一种用于在主计算机和外围存储器之间传送数据的方法，包括以下步骤：（a）从主机接收数据; （b）确定数据中是否存在转义命令; （c）如果数据中不存在转义命令，则将数据写入外围存储介质; 以及（d）如果数据中存在转义命令，则相对于外围存储器执行至少一个命令。还公开了一种用于控制盘驱动单元的方法，包括以下步骤：（a）在主计算机上确定要用盘驱动单元执行的当前动作; （b）如果当前动作是格式化动作，则基于由主计算机提供的输出数据来格式化与磁盘驱动器单元接合的盘的轨道; （c）如果当前动作是写入动作，则基于由主计算机提供的输出数据在盘上写入扇区; 以及（d）如果动作是读取动作，则读取磁盘的扇区并将输入信息传送到主计算机。转义代码用于将“正常”数据与“特殊”数据进行区分。本发明的磁盘驱动器控制器包括响应于主计算机的数据总线的数字逻辑，并且可操作地基于数据总线开发数据类型总线，其中数据类型总线用于指定多个数据类型之一，以及响应于数据总线和数据类型总线的转换器，并且可操作以向盘驱动器单元机构提供串行数据。

3. 发明授权

US5167024A Power management for a laptop computer with slow and sleep modes 失效
标题翻译：具有慢和睡眠模式的笔记本电脑的电源管理
公开(公告)号：US5167024A
公开(公告)日：1992-11-24
申请号：US845781
申请日：1992-03-05
申请人： R. Steven Smith , Mike S. Hanlon , Robert L. Bailey
发明人： R. Steven Smith , Mike S. Hanlon , Robert L. Bailey
IPC分类号： G06F1/32 , H02J7/00
CPC分类号： G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/325 , G06F1/3287 , H02J7/0063 , Y02B60/1217 , Y02B60/1282
摘要： A power manager within a portable laptop computer provides power and clocking control to various units within the computer in order to conserve battery power. Transistor switches controlled by the power manager control the distribution of power and/or clock signals to the various units within the computer. The power manager includes a software routine for continually monitoring the various units and when these units are either not needed and/or not currently in use, power and/or clock signals are removed from a given unit.
摘要翻译：便携式笔记本电脑内的电源管理器为计算机内的各种单元提供电源和时钟控制，以节省电池电量。由电源管理器控制的晶体管开关控制电源和/或时钟信号分配给计算机内的各种单元。功率管理器包括用于连续监视各种单元的软件程序，并且当这些单元不需要和/或当前不使用时，从给定单元去除功率和/或时钟信号。

4. 发明授权

US07130308B2 Data path architecture for a LAN switch 有权
标题翻译： LAN交换机的数据路径体系结构
公开(公告)号：US07130308B2
公开(公告)日：2006-10-31
申请号：US09952274
申请日：2001-09-13
申请人： Stephen R. Haddock , Justin N. Chueh , David K. Parker , Herb Schneider , R. Steven Smith , Erik R. Swenson
发明人： Stephen R. Haddock , Justin N. Chueh , David K. Parker , Herb Schneider , R. Steven Smith , Erik R. Swenson
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/2441 , H04L45/745 , H04L47/2416 , H04L47/50 , H04L47/6215 , H04L47/627 , H04L49/3018 , H04L49/351 , H04L49/352 , H04L49/354
摘要： A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers to hold the portion of the data packets exchanged with the corresponding medium access controller. Each data path controller has a selector that selects the buffer from which to exchange the portion of the data packets with the central shared memory and control logic that controls the selector to concurrently select the buffer corresponding to the same medium access controller.
摘要翻译：具有中央共享存储器和多个介质访问控制器的分组交换设备，每个媒体接入控制器都耦合到通信介质以交换数据分组;以及控制器，其经由数据路径耦合到每个介质访问控制器，以与介质访问控制器交换数据分组。控制器具有多个数据路径控制器，每个数据路径控制器连接到每个介质访问控制器，以将介质访问控制器的数据分组的相应部分交换。数据路径控制器各自具有多个缓冲器以保持与相应的介质访问控制器交换的数据分组的部分。每个数据路径控制器具有选择器，该选择器选择用于与中央共享存储器交换数据分组的一部分的缓冲器以及控制选择器同时选择对应于相同介质访问控制器的缓冲器的控制逻辑。

5. 发明授权

US06295299B1 Data path architecture for a LAN switch 失效
标题翻译： LAN交换机的数据路径体系结构
公开(公告)号：US06295299B1
公开(公告)日：2001-09-25
申请号：US09016017
申请日：1998-01-30
申请人： Stephen R. Haddock , Justin N. Chueh , David K. Parker , Herb Schneider , R. Steven Smith , Erik R. Swenson
发明人： Stephen R. Haddock , Justin N. Chueh , David K. Parker , Herb Schneider , R. Steven Smith , Erik R. Swenson
IPC分类号： H04L1256
CPC分类号： H04L47/2441 , H04L45/745 , H04L47/2416 , H04L47/50 , H04L47/6215 , H04L47/627 , H04L49/3018 , H04L49/351 , H04L49/352 , H04L49/354
摘要： A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets therewith, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller via a separate and like portion of the data path to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers each connected to one of the medium access controllers to which the data path controller is connected, to hold the portion of the data packets exchanged with the corresponding medium access controller. Each data path controller has a selector that selects the buffer from which to transmit or receive the portion of the data packets with the central shared memory and control logic that controls the selector to concurrently select the buffer corresponding to the same medium access controller. A comparison engine associated with each data path controller detects the slice of a field in a data packet buffered in the corresponding data path controller and computes a hashing function on the contents of the slice of the field to generate a hash key. A packet forwarding controller reads one or more entries from a hash bucket in a forwarding database indexed by the hash key and sends the entries to the comparison logic. The comparison logic compares the slice of the field in the buffer to each of the entries and returns the results of the compare to a packet forwarding controller. The forwarding controller then forwards, filters or identifies packets based on the results of the comparisons done on each slice of a field in the packets.
摘要翻译：一种具有中央共享存储器和多个介质访问控制器的分组交换设备，每个媒体接入控制器都耦合到通信介质以与其通信以交换数据分组;以及控制器，其经由数据路径耦合到每个介质访问控制器，以与介质访问控制器交换数据分组。控制器具有多个数据路径控制器，每个数据路径控制器经由数据路径的单独和相似的部分连接到每个介质访问控制器，以将数据分组的相应部分与介质访问控制器交换。数据路径控制器各自具有多个缓冲器，每个缓冲器连接到数据路径控制器连接到的一个介质访问控制器，以保持与相应介质访问控制器交换的数据分组的部分。每个数据路径控制器具有一个选择器，该选择器选择用中央共享存储器发送或接收数据分组的一部分的缓冲器，控制逻辑控制选择器同时选择对应于同一介质访问控制器的缓冲器。与每个数据路径控制器相关联的比较引擎检测缓冲在相应的数据路径控制器中的数据包中的字段的切片，并且对该字段的内容计算散列函数以生成散列密钥。分组转发控制器从散列密钥索引的转发数据库中的哈希桶中读取一个或多个条目，并将条目发送到比较逻辑。比较逻辑将缓冲器中的字段的切片与每个条目进行比较，并将比较的结果返回给分组转发控制器。然后，转发控制器基于在分组中的字段的每个片段上进行的比较的结果来转发，过滤或标识分组。

6. 发明授权

US5237674A Self identifying scheme for memory module including circuitry for identfying accessing speed 失效
标题翻译：用于存储模块的自识别方案，包括用于识别访问速度的电路
公开(公告)号：US5237674A
公开(公告)日：1993-08-17
申请号：US713639
申请日：1991-06-10
申请人： Rodger Mohme , Jerome Okun , R. Steven Smith , Michael De La Cruz
发明人： Rodger Mohme , Jerome Okun , R. Steven Smith , Michael De La Cruz
IPC分类号： G06F12/06
CPC分类号： G06F12/0684
摘要： A self-identifying scheme which permits a variety of integrated circuit semiconductor memory modules to inform a host processor as to each individual memory accessing speed or accessing time. Pre-encoded circuits within each memory module generate a coded signal when that module is selected by the host processor. The coded signal identifies the type of memory accessed, permitting the host processor to transfer information at a rate determined by the memory accessed.
摘要翻译：允许各种集成电路半导体存储器模块向主机处理器通知每个单独的存储器访问速度或访问时间的自识别方案。当主机处理器选择该模块时，每个存储器模块内的预编码电路产生编码信号。编码信号识别所访问的存储器的类型，允许主处理器以由访问的存储器确定的速率传送信息。

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