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1. 发明申请

US20190042510A1 TIMER CONTROL FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS COMPONENTS IMPLEMENTED WITH THUNDERBOLT CONTROLLERS 审中-公开
公开(公告)号：US20190042510A1
公开(公告)日：2019-02-07
申请号：US15870679
申请日：2018-01-12
申请人： Christopher Wing Hong Ngau , Hooi Kar Loo , Poh Thiam Teoh , Shashitheren Kerisnan , Maxim Dan , Chee Siang Chow
发明人： Christopher Wing Hong Ngau , Hooi Kar Loo , Poh Thiam Teoh , Shashitheren Kerisnan , Maxim Dan , Chee Siang Chow
IPC分类号： G06F13/40 , G06F13/42 , H04B10/27
摘要： Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

2. 发明授权

US09270555B2 Power mangement techniques for an input/output (I/O) subsystem 有权
标题翻译：输入/输出（I / O）子系统的电力管理技术
公开(公告)号：US09270555B2
公开(公告)日：2016-02-23
申请号：US13175557
申请日：2011-07-01
申请人： Poh Thiam Teoh , Su Wei Lim
发明人： Poh Thiam Teoh , Su Wei Lim
IPC分类号： H04L12/26 , H04L12/12
CPC分类号： H04L43/0876 , H04L12/12 , H04L43/0882 , Y02B60/1235 , Y02D50/40
摘要： A method and system to improve the power management for an I/O subsystem. In one embodiment of the invention, the power management of an upstream port of the I/O subsystem is improved by increasing the upstream link utilization when the upstream port is an active power state and by increasing or prolonging the power saving period of the upstream port when the upstream port is in a low power state.
摘要翻译：一种改进I / O子系统电源管理的方法和系统。在本发明的一个实施例中，通过在上游端口是有功功率状态时增加上游链路利用率，并且通过增加或延长上游端口的节电周期来提高I / O子系统的上行端口的功率管理当上游端口处于低功率状态时。

3. 发明申请

US20140195835A1 SYSTEM AND METHOD FOR PROVIDING POWER SAVINGS IN A PROCESSOR ENVIRONMENT 有权
标题翻译：在处理器环境中提供节电的系统和方法
公开(公告)号：US20140195835A1
公开(公告)日：2014-07-10
申请号：US13734577
申请日：2013-01-04
申请人： Sun Zheng E. , Ting Lok Song , Poh Thiam Teoh , Jennifer Chin , Say Cheong Gan , Sujea Lim , Su Wei Lim
发明人： Sun Zheng E. , Ting Lok Song , Poh Thiam Teoh , Jennifer Chin , Say Cheong Gan , Sujea Lim , Su Wei Lim
IPC分类号： G06F1/32
CPC分类号： G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.
摘要翻译：本文描述的特定实施例可以提供一种方法，其包括断电根端口; 通过中央处理单元（CPU）向根端口发起第一下游循环; 识别CPU的加电活动; 并且触发用于电力状态的退出流，同时向根端口发送第二下游循环。在更具体的实施例中，用于功率状态的出口流的触发和将第二下游循环发送到根端口以基本上平行的方式发生。另外，在CPU上电并发送第二个下游周期之前，可以将根据端口发送预取指示符以触发退出流。

4. 发明授权

US09558030B2 Method, apparatus, and system to handle transactions received after a configuration change request 有权
标题翻译：方法，设备和系统来处理配置更改请求后收到的事务
公开(公告)号：US09558030B2
公开(公告)日：2017-01-31
申请号：US13997619
申请日：2011-11-09
申请人： Su Wei Lim , Kah Meng Yeem , Poh Thiam Teoh , Hooi Kar Loo , Sujea Lim
发明人： Su Wei Lim , Kah Meng Yeem , Poh Thiam Teoh , Hooi Kar Loo , Sujea Lim
IPC分类号： G06F3/00 , G06F5/00 , G06F9/44 , G06F9/46 , G06F3/06 , G06F5/06 , G06F13/16 , G06F5/10 , G06F5/12 , G06F12/00 , G06F13/14
CPC分类号： G06F9/46 , G06F3/0659 , G06F5/06 , G06F5/10 , G06F5/12 , G06F9/461 , G06F9/466 , G06F12/00 , G06F13/14 , G06F13/1621 , G06F13/1642 , G06F13/36
摘要： Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration change request; and handling the first and second transactions.
摘要翻译：用于处理在配置请求之后接收的事务的方法，装置和系统，所述方法例如包括：通过事务处理逻辑块接收配置改变请求; 响应于所述配置改变请求，由所述事务处理逻辑块执行配置更改，其中所述逻辑块将在接收到所述配置改变请求之前处理在接收到所述配置改变请求之前接收到的事务; 在接收到配置改变请求之前，由交易处理逻辑块接收第一事务; 在接收到配置更改请求之后并且在配置改变完成之前，通过事务处理逻辑块接收第二事务; 基于相对于接收到配置改变请求而接收到第一和第二事务的顺序，将第一事务与第二事务区分开; 并处理第一次和第二次交易。

5. 发明申请

US20140195830A1 SYSTEM AND METHOD FOR POWER MANAGEMENT 有权
标题翻译：电力管理系统与方法
公开(公告)号：US20140195830A1
公开(公告)日：2014-07-10
申请号：US13734612
申请日：2013-01-04
申请人： Jennifer Chin , Su Wei Lim , Poh Thiam Teoh , Ting Lok Song , Sun Zheng E , Say Cheong Gan , Sujea Lim , Ming Yi Lim
发明人： Jennifer Chin , Su Wei Lim , Poh Thiam Teoh , Ting Lok Song , Sun Zheng E , Say Cheong Gan , Sujea Lim , Ming Yi Lim
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/1626 , G06F1/3206 , G06F1/3218 , G06F1/3243 , G06F13/4282 , G06F2213/0026 , Y02D10/151 , Y02D10/152
摘要： Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
摘要翻译：本文描述的特定实施例可以提供一种用于管理至少一个处理器的功率的方法，该处理器包括评估与电子设备相关联的多个端口; 确定与所述端口中的至少一个相关联的特定引脚没有接收到信号; 禁用与所述电子设备相关联的静噪功能; 以及与电子设备的物理层（PHY）相关联的门控功率。

6. 发明授权

US08601198B2 Controllable transaction synchronization for merging peripheral devices 有权
标题翻译：用于合并外围设备的可控事务同步
公开(公告)号：US08601198B2
公开(公告)日：2013-12-03
申请号：US13174436
申请日：2011-06-30
申请人： Chee Hak Teh , Chai Huat Gan , Poh Thiam Teoh , Mary Siaw See Yeoh , Su Wei Lim
发明人： Chee Hak Teh , Chai Huat Gan , Poh Thiam Teoh , Mary Siaw See Yeoh , Su Wei Lim
IPC分类号： G06F13/20 , G06F13/38
CPC分类号： G06F13/385 , G06F13/4022
摘要： Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router.Embodiments of the invention allow for devices to be “merged” into a single device for the host OS. For example, a peripheral devices coupled to the host system via a PCIe link may be “merged” with a peripheral devices coupled to the host system via another PCIe link or a SATA link.
摘要翻译：本发明的实施例描述了能够将PCIe设备和另一单独的设备关联到相同设备标识符（例如，设备号码）的主机系统。周期路由模块或逻辑将识别涉及设备标识符的I / O事务，并将事务路由到一个或两个设备（或者在某些情况下，将I / O事务标识为配置事务，并且简单地更新循环路由模块/逻辑）。在本发明的一个实施例中，主机系统的根端口被配置为作为上述循环路由器进行操作。本发明的实施例允许将设备“合并”成用于主机OS的单个设备。例如，经由PCIe链路耦合到主机系统的外围设备可以经由另一PCIe链路或SATA链路与耦合到主机系统的外围设备“合并”。

7. 发明申请

US20190041936A1 METHOD, APPARATUS, AND SYSTEM FOR POWER MANAGEMENT ON A CPU DIE VIA CLOCK REQUEST MESSAGING PROTOCOL 审中-公开
公开(公告)号：US20190041936A1
公开(公告)日：2019-02-07
申请号：US15870629
申请日：2018-01-12
申请人： Poh Thiam Teoh , Mikal C. Hunsaker , Su Wei Lim , Gim Chong Lee , Hooi Kar Loo , Shashitheren Kerisnan , Siang Lin Tan , Ming Chew Lee , Ngeok Kuan Wai , Li Len Lim
发明人： Poh Thiam Teoh , Mikal C. Hunsaker , Su Wei Lim , Gim Chong Lee , Hooi Kar Loo , Shashitheren Kerisnan , Siang Lin Tan , Ming Chew Lee , Ngeok Kuan Wai , Li Len Lim
IPC分类号： G06F1/26 , G06F13/42 , G06F1/10
摘要： Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

8. 发明授权

US09367500B2 Apparatus for multiple bus master engines to share the same request channel to a pipelined backbone 有权
标题翻译：用于多总线主机引擎的共享相同请求信道到流水线骨干网的装置
公开(公告)号：US09367500B2
公开(公告)日：2016-06-14
申请号：US13997623
申请日：2011-11-09
申请人： Ngek Leong Guok , Kah Meng Yeem , Poh Thiam Teoh , Jennifer Chin , Su Wei Lim
发明人： Ngek Leong Guok , Kah Meng Yeem , Poh Thiam Teoh , Jennifer Chin , Su Wei Lim
IPC分类号： G06F13/364 , H04L12/28
CPC分类号： G06F13/364 , H04L12/28
摘要： In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request.
摘要翻译：根据本文公开的实施例，是使得多个总线主机引擎能够将共同的请求信道共享到流水线主干的机制，包括：在代理总线接口处从多个主机接收多个未定义的授权请求，每个请求访问主干通过公共请求通道连接; 确定哪些无效的授权请求首先作为最终授权请求发出; 将用于最终授权请求的主标识符代码存储到FIFO缓冲器中，所述主标识符代码将所述最终许可请求与所述多个主器件中的发布主机相关联; 等待骨干资助; 以及向代理总线接口呈现用于最终授权请求的主标识符代码，其中，所述代理总线接口响应于所述骨干授权，经由骨干进行处理的命令和数据，以完成最终授权请求。

9. 发明授权

US09268568B2 Method and apparatus for agent interfacing with pipeline backbone to locally handle transactions while obeying ordering rule 有权
标题翻译：用于代理与流水线骨干接口的方法和装置，以便在遵守排序规则的同时处理事务
公开(公告)号：US09268568B2
公开(公告)日：2016-02-23
申请号：US13997628
申请日：2011-11-09
申请人： Ngek Leong Guok , Kah Meng Yeem , Poh Thiam Teoh , Su Wei Lim
发明人： Ngek Leong Guok , Kah Meng Yeem , Poh Thiam Teoh , Su Wei Lim
IPC分类号： G06F3/00 , G06F13/00 , G06F9/30 , G06F13/14 , G06F15/163 , H04L29/06
CPC分类号： G06F9/30043 , G06F13/14 , G06F15/163 , H04L69/12
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule including, for example, receiving a transaction which requests access to a backbone; decoding routing destination information from the transaction received, in which the decoded routing destination information designates the transaction to be processed either locally or processed via the backbone; storing the decoded routing destination information and the transaction into a First-In-First-Out (FIFO) buffer; retrieving the decoded routing destination information and the transaction from the FIFO buffer; and processing the transaction locally or via the backbone based on the decoded routing destination information retrieved from the FIFO buffer with the transaction.
摘要翻译：根据本文公开的实施例，提供了用于使得代理与流水线骨干网接口的本地处理事务的方法，系统和装置，同时服从排序规则，包括例如接收请求访问主干的事务; 从所接收的事务解码路由目的地信息，其中解码的路由目的地信息指定要在本地处理或经由骨干处理的交易; 将解码的路由目的地信息和交易存储到先进先出（FIFO）缓冲器中; 从FIFO缓冲器检索解码的路由目的地信息和事务; 并且基于从具有交易的FIFO缓冲器检索的解码的路由目的地信息，在本地处理或经由骨干处理事务。

10. 发明申请

US20140207986A1 APPARATUS FOR MULTIPLE BUS MASTER ENGINES TO SHARE THE SAME REQUEST CHANNEL TO A PIPELINED BACKBONE 有权
标题翻译：多台总线主机的设备将相同的请求信道分配给一个管道的后座
公开(公告)号：US20140207986A1
公开(公告)日：2014-07-24
申请号：US13997623
申请日：2011-11-09
申请人： Ngek Leong Guok , Kah Meng Yeem , Poh Thiam Teoh , Jennifer Chin , Su Wei Lim
发明人： Ngek Leong Guok , Kah Meng Yeem , Poh Thiam Teoh , Jennifer Chin , Su Wei Lim
IPC分类号： G06F13/364 , G06F13/16
CPC分类号： G06F13/364 , H04L12/28
摘要： In accordance with embodiments disclosed herein are mechanisms for enabling multiple bus master engines to share the same request channel to a pipelined backbone including: receiving a plurality of unarbitrated grant requests at an agent bus interface from a plurality of masters, each requesting access to a backbone connected via a common request channel; determining which of the unarbitrated grant requests is to issue first as a final grant request; storing a master identifier code for the final grant request into a FIFO buffer, the master identifier code associating the final grant request with the issuing master among the plurality of masters; waiting for a backbone grant; and presenting the master identifier code for the final grant request to an agent bus interface, wherein the agent bus interface communicates a command and data for processing via a backbone responsive to the backbone grant to fulfill the final grant request.
摘要翻译：根据本文公开的实施例，是使得多个总线主机引擎能够将共同的请求信道共享到流水线主干的机制，包括：在代理总线接口处从多个主机接收多个非占用授权请求，每个请求访问主干通过公共请求通道连接; 确定哪些无效的授权请求首先作为最终授权请求发出; 将用于最终授权请求的主标识符代码存储到FIFO缓冲器中，所述主标识符代码将所述最终许可请求与所述多个主器件中的发布主机相关联; 等待骨干资助; 以及向代理总线接口呈现用于最终授权请求的主标识符代码，其中，所述代理总线接口响应于所述骨干授权，经由骨干进行处理的命令和数据，以完成最终授权请求。

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