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1. 发明授权

US08828846B2 Method of computing a width of a scribe region based on a bonding structure that extends into the scribe reigon in a wafer-level chip scale (WLCSP) packaging 有权
标题翻译：基于在晶片级芯片尺寸（WLCSP）封装中延伸到划线区域的接合结构来计算划线区域的宽度的方法
公开(公告)号：US08828846B2
公开(公告)日：2014-09-09
申请号：US13191349
申请日：2011-07-26
申请人： Philip S. Ng
发明人： Philip S. Ng
IPC分类号： H01L21/00 , H01L23/31 , H01L21/56 , H01L23/00
CPC分类号： H01L21/561 , H01L23/3114 , H01L24/13 , H01L2224/131 , H01L2224/94 , H01L2924/14 , H01L2924/014 , H01L2224/11 , H01L2924/00
摘要： The disclosed WLCSP solution overcomes the limitations of fan-out WLCSP solutions, and other conventional solutions for WLCSP for small, high volume die, by increasing the width of scribe regions between die on a semiconductor substrate to accommodate bonding structures (e.g., solder balls) that partially extend beyond peripheral edges of the die. The scribe regions can be widened in x and y directions on the wafer. The widened scribe regions can be incorporated into the design of the mask set.
摘要翻译：所公开的WLCSP解决方案通过增加半导体衬底上的芯片之间的划线区域的宽度以适应接合结构（例如，焊球）来克服扇出WLCSP解决方案以及用于小型，高容量管芯的WLCSP的其他传统解决方案的局限性，其部分地延伸超过模具的周边边缘。划片区域可以在晶片上沿x和y方向加宽。扩大的划线区可以并入掩模组的设计中。

2. 发明授权

US07868660B2 Serial communications bus with active pullup 有权
标题翻译：具有主动上拉电阻的串行通信总线
公开(公告)号：US07868660B2
公开(公告)日：2011-01-11
申请号：US11379473
申请日：2006-04-20
申请人： Philip S. Ng , Jinshu Son
发明人： Philip S. Ng , Jinshu Son
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721 , H03K19/01742
摘要： A dual-wire communications bus circuit, compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to one or more slave devices and a second line to carry a clock signal between the devices. A pullup resistor is located in each part of the communications bus circuit; the pullup resistor in the first part couples to the first line of the communications bus and the pullup resistor in the second part couples to the second line of the communications bus. To improve data throughput and reduce noise, an active pullup device, working in conjunction with the pullup resistor, is located in each part of the communications bus circuit, providing a high logic level on at least one of the communications bus lines.
摘要翻译：与现有的双线总线协议兼容的双线通信总线电路包括通信总线电路的第一和第二部分以耦合到通信总线。总线具有用于承载来自主设备的数据信号到一个或多个从设备的第一行，以及用于在设备之间传送时钟信号的第二行。上拉电阻位于通信总线电路的每个部分; 第一部分中的上拉电阻耦合到通信总线的第一行，并且第二部分中的上拉电阻耦合到通信总线的第二行。为了提高数据吞吐量并降低噪声，与通信总线电路的每个部分配置的与上拉电阻一起工作的有源上拉器件位于通信总线电路的每个部分中，在至少一个通信总线上提供高逻辑电平。

3. 发明申请

US20090168586A1 CIRCUIT TO CONTROL VOLTAGE RAMP RATE 有权
标题翻译：电路控制电压RAMP RATE
公开(公告)号：US20090168586A1
公开(公告)日：2009-07-02
申请号：US12398805
申请日：2009-03-05
申请人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey Ming-Hung Tsai , Tin-Wai Wong , Tsung-Ching Wu
发明人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey Ming-Hung Tsai , Tin-Wai Wong , Tsung-Ching Wu
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G11C16/12
摘要： A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
摘要翻译：一种编程电路和方法，用于以增量的方式对受控或预定的电压脉冲施加电荷转移到非易失性存储单元的浮置栅极，或者从非易失性存储单元的浮动栅极流出，以控制栅极氧化物两端的整体电压。高于传输阈值电压的电压（例如高于隧道阈值电压）以逐步电荷转移方式施加到浮动栅极或从浮动栅极施加到低于薄氧化物损伤阈值的电压极限。控制整体电压可避免氧化物破坏，提高可靠性。

4. 发明授权

US07982499B2 Capacitive node isolation for electrostatic discharge circuit 有权
标题翻译：静电放电电路的电容节点隔离
公开(公告)号：US07982499B2
公开(公告)日：2011-07-19
申请号：US11459734
申请日：2006-07-25
申请人： Philip S. Ng
发明人： Philip S. Ng
IPC分类号： H03K19/0175
CPC分类号： G01R31/002
摘要： Capacitive node isolation circuitry in an integrated circuit eliminates the creation of hot spots (stored charge) on high capacitive nodes during a test of electrostatic discharge (ESD) protection circuitry of the integrated circuit or during any ESD event occurring while the integrated circuit is in a standby mode. The isolation circuitry includes a standby mode logic circuit responsive to a standby mode signal received at one of its inputs and provides an output signal to a gate of an active switching device located in a path between an external pin of the integrated circuit and the internal high capacitive node. The output signal keeps the active switching device turned off for the duration of the ESD test or ESD event. The standby mode logic circuit transparently passes an input logic signal to the active switching device whenever the integrated circuit is in a normal operating mode.
摘要翻译：集成电路中的电容节点隔离电路消除了在集成电路的静电放电（ESD）保护电路的测试期间或在集成电路处于ESD状态期间发生的任何ESD事件期间在高容性节点上产生热点（存储电荷）待机模式。隔离电路包括响应于在其输入端之一处接收的待机模式信号的待机模式逻辑电路，并将输出信号提供给位于集成电路的外部引脚和内部高电平之间的路径中的有源开关器件的栅极电容节点。在ESD测试或ESD事件期间，输出信号保持有源开关器件关闭。只要集成电路处于正常工作模式，待机模式逻辑电路将输入逻辑信号透明地传递到有源开关装置。

5. 发明申请

US20100149710A1 SNAP-BACK TOLERANT INTEGRATED CIRCUITS 有权
标题翻译： SNAP-BACK容差集成电路
公开(公告)号：US20100149710A1
公开(公告)日：2010-06-17
申请号：US12334155
申请日：2008-12-12
申请人： Philip S. Ng
发明人： Philip S. Ng
IPC分类号： H02H9/04
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON) state. An auxiliary circuit coupled to a source node of the first NMOS transistor may be configured to provide a bias potential at the source node of the first NMOS transistor, when the first NMOS transistor is in a non-conducting state (OFF).
摘要翻译：提供了用于防止MOS集成电路的NMOS晶体管中的回耦电流的方法和电路。示例性实施例可以包括防止包括具有相关联的寄生双极晶体管的第一NMOS晶体管的电路中的回耦电流。第二NMOS晶体管可以与第一NMOS晶体管串联连接。第二NMOS晶体管的栅极节点可以耦合到偏置节点，使得第二NMOS晶体管处于导通（ON）状态。耦合到第一NMOS晶体管的源节点的辅助电路可以被配置为当第一NMOS晶体管处于非导通状态（OFF）时，在第一NMOS晶体管的源极节点处提供偏置电位。

6. 发明申请

US20100064083A1 COMMUNICATIONS DEVICE WITHOUT PASSIVE PULLUP COMPONENTS 审中-公开
标题翻译：没有被动抽头组件的通信设备
公开(公告)号：US20100064083A1
公开(公告)日：2010-03-11
申请号：US12619545
申请日：2009-11-16
申请人： Philip S. Ng , Jinshu Son
发明人： Philip S. Ng , Jinshu Son
IPC分类号： G06F13/00
CPC分类号： G06F13/4077 , G06F2213/0016
摘要： A dual-wire communications bus circuit, compatible with existing two-wire protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to a slave device and a second line to carry a clock signal between the devices. To improve data throughout and reduce noise, an active pullup device is located in at least one part of the communications bus circuit, the active pullup device in the first part of the of the communications bus circuit couples to the first line and an optional active pullup device in the second part couples to the second line of the communications bus. Each active pullup device may provide a high logic level on one of the communications bus lines.
摘要翻译：与现有的双线协议兼容的双线通信总线电路包括通信总线电路的第一和第二部分以耦合到通信总线。总线具有用于承载从主设备到从设备的数据信号的第一行，以及用于在设备之间携带时钟信号的第二行。为了改善数据并减少噪声，有源上拉器件位于通信总线电路的至少一部分中，通信总线电路的第一部分中的有源上拉器件耦合到第一条线路，并且可选的有源上拉电路第二部分中的设备耦合到通信总线的第二行。每个有源上拉装置可以在通信总线之一上提供高逻辑电平。

7. 发明申请

US20080298385A1 DEVICE AND METHOD OF SUPPLYING POWER TO TARGETS ON SINGLE-WIRE INTERFACE 有权
标题翻译：在单线接口上向目标提供电力的装置和方法
公开(公告)号：US20080298385A1
公开(公告)日：2008-12-04
申请号：US11754879
申请日：2007-05-29
申请人： Philip S. Ng , Ken Ye
发明人： Philip S. Ng , Ken Ye
IPC分类号： H04L12/413
CPC分类号： H04L12/40045 , H04L12/40032 , H04L2012/40273
摘要： A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from the single-wire interface at a power-supply voltage level and charges the charge storage device to the same level. Non-communication periods produce a charging period sufficient for the charge storage device to attain the power-supply voltage level.
摘要翻译：单线接口通信系统能够在耦合到系统的设备之间提供信号和电力的电通信。耦合到单线接口的是至少一个包含PMOS晶体管，电荷存储装置，控制PMOS晶体管的逆变器和目标器件功能的目标器件。电荷存储装置为目标装置功能和逆变器提供电力。 PMOS晶体管以电源电压电平从单线接口接收电力，并将电荷存储装置充电至同一电平。非通信周期产生足以使电荷存储装置获得电源电压电平的充电时段。

8. 发明申请

US20080159432A1 COMMUNICATION PROTOCOL METHOD AND APPARATUS FOR A SINGLE WIRE DEVICE 有权
标题翻译：一种单线设备的通信协议方法和设备
公开(公告)号：US20080159432A1
公开(公告)日：2008-07-03
申请号：US11618542
申请日：2006-12-29
申请人： Philip S. Ng
发明人： Philip S. Ng
IPC分类号： H04L29/06 , H04L7/00 , H04L27/00
CPC分类号： H04L7/02 , H04L7/027 , H04L7/0276 , H04L7/0331 , H04L7/044
摘要： The present invention is a noise tolerant communication protocol device and method where a clock signal input triggers ail internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during periods around edges of changing data values. Therefore, error detection and correction circuitry is not required. A time reference pulse, produced by a bus master, is measured by the protocol device to determine a data transmission rate by the master. The timing of sampling of input signaling from the master is determined by the protocol device from measurement of the time reference pulse magnitude.
摘要翻译：本发明是一种噪声容限通信协议装置和方法，其中时钟信号输入触发集成电路中的内部延迟时钟。数据呈现给输入引脚，并根据内部延迟时钟在下一个外部时钟脉冲之前采样。数据脉冲值由输入信号电压电平而不是脉冲长度区分。数据位的采样被推迟直到信号电平最可能稳定，从而避免在改变数据值的边缘周期期间的采样。因此，不需要错误检测和校正电路。由总线主机产生的时间参考脉冲由协议设备测量以确定主设备的数据传输速率。通过协议设备从时间基准脉冲幅度的测量来确定来自主机的输入信令的采样定时。

9. 发明授权

US07307898B2 Method and apparatus for implementing walkout of device junctions 有权
公开(公告)号：US07307898B2
公开(公告)日：2007-12-11
申请号：US11291498
申请日：2005-11-30
申请人： Philip S. Ng , Jinshu Son , Johnny Chan
发明人： Philip S. Ng , Jinshu Son , Johnny Chan
IPC分类号： G11C5/14 , G11C7/10 , G11C7/00 , G11C16/04
CPC分类号： G11C5/145 , G11C5/147
摘要： A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high-voltage output circuits to the output of the high-voltage charge pump circuit.

10. 发明授权

US07102950B2 Fuse data storage system using core memory 有权
标题翻译：保险丝数据存储系统采用核心内存
公开(公告)号：US07102950B2
公开(公告)日：2006-09-05
申请号：US10910038
申请日：2004-08-02
申请人： Jinshu Son , Liqi Wang , Minh V. Le , Philip S. Ng
发明人： Jinshu Son , Liqi Wang , Minh V. Le , Philip S. Ng
IPC分类号： G11C7/00
CPC分类号： G11C17/18 , G11C16/20 , G11C2216/30
摘要： Fuse data used to configure ancillary circuits used with a non-volatile serial memory core are stored in locations within the memory core. As a first opcode or word is sent on a serial bus to the memory, a logic circuit intercepts the word and generates read fuse enable pulses that fetch the fuse data and configure the ancillary circuits before the last bit of the first command byte arrives. If a read operation is designated, the memory circuits are configured to read. If a write operation is designated, further fuse data is fetched from the memory core to configure ancillary circuits for writing. The fuse data is written to the memory core at the time of circuit manufacture thereby obviating the need for separate storage locations.
摘要翻译：用于配置与非易失性串行存储器核心一起使用的辅助电路的保险丝数据存储在存储器核心内的位置。当串行总线上的第一个操作码或字被发送到存储器时，一个逻辑电路拦截该字并产生读保险丝使能脉冲，该脉冲在第一命令字节的最后一位到达之前提取熔丝数据并配置辅助电路。如果指定了读取操作，则存储器电路被配置为读取。如果指定写入操作，则从存储器核心获取进一步的熔丝数据以配置用于写入的辅助电路。在电路制造时，熔丝数据被写入存储器核心，从而避免了对单独的存储位置的需要。

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