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1. 发明申请

US20090168586A1 CIRCUIT TO CONTROL VOLTAGE RAMP RATE 有权
标题翻译：电路控制电压RAMP RATE
公开(公告)号：US20090168586A1
公开(公告)日：2009-07-02
申请号：US12398805
申请日：2009-03-05
申请人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey Ming-Hung Tsai , Tin-Wai Wong , Tsung-Ching Wu
发明人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey Ming-Hung Tsai , Tin-Wai Wong , Tsung-Ching Wu
IPC分类号： G11C5/14 , G05F1/10
CPC分类号： G11C16/12
摘要： A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
摘要翻译：一种编程电路和方法，用于以增量的方式对受控或预定的电压脉冲施加电荷转移到非易失性存储单元的浮置栅极，或者从非易失性存储单元的浮动栅极流出，以控制栅极氧化物两端的整体电压。高于传输阈值电压的电压（例如高于隧道阈值电压）以逐步电荷转移方式施加到浮动栅极或从浮动栅极施加到低于薄氧化物损伤阈值的电压极限。控制整体电压可避免氧化物破坏，提高可靠性。

2. 发明授权

US07233528B2 Reduction of programming time in electrically programmable devices 有权
标题翻译：减少电可编程器件中的编程时间
公开(公告)号：US07233528B2
公开(公告)日：2007-06-19
申请号：US11188612
申请日：2005-07-25
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data “one” value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data “zero” is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data “one” is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data “one” bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data “one” values are to be programmed in parallel.
摘要翻译：闪存编程过程包含每个字节位单元的两个电荷泵。在每个位单元中放置数据“一个”值会擦除整个存储器件。在编制每个单元格之前，仔细检查一个预期的数据内容。如果将数据“零”应用于位单元，则电荷泵接合以偏置电池并激活热电子注入过程以影响编程。如果将数据“1”应用于比特单元，则不进行编程活动，并且该处理在数据结构中递增到下一比特单元。因此，总编程时间与要编程的数据“1”位成比例地减小。当一个以上的电荷泵与数据结构并联时，当两个数据“一个”值被并行编程时，总编程时间进一步减少。

3. 发明授权

US07512008B2 Circuit to control voltage ramp rate 有权
标题翻译：电路控制电压斜坡率
公开(公告)号：US07512008B2
公开(公告)日：2009-03-31
申请号：US11291606
申请日：2005-11-30
申请人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey Ming-Hung Tsai , Tin-Wai Wong , Tsung-Ching Wu
发明人： Johnny Chan , Philip S. Ng , Alan L. Renninger , Jinshu Son , Jeffrey Ming-Hung Tsai , Tin-Wai Wong , Tsung-Ching Wu
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/12
摘要： A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
摘要翻译：一种编程电路和方法，用于以增量的方式对受控或预定的电压脉冲施加电荷转移到非易失性存储单元的浮置栅极，或者从非易失性存储单元的浮动栅极流出，以控制栅极氧化物两端的整体电压。高于传输阈值电压的电压（例如高于隧道阈值电压）以逐步电荷转移方式施加到浮动栅极或从浮动栅极施加到低于薄氧化物损伤阈值的电压极限。控制整体电压可避免氧化物破坏，提高可靠性。

4. 发明授权

US07863959B2 Apparatus and methods for a high-voltage latch 有权
标题翻译：高电压锁存装置及方法
公开(公告)号：US07863959B2
公开(公告)日：2011-01-04
申请号：US12538766
申请日：2009-08-10
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： H03K3/356
CPC分类号： H03K3/356182 , G11C16/08 , G11C16/12
摘要： Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.
摘要翻译：一些实施例包括具有存储节点的设备和耦合到存储节点的锁存电路，以锁定在设备的第一模式和第二模式之一期间提供给存储节点的数据。锁存电路包括耦合在第一电压节点和第二电压节点之间的第一晶体管，第二晶体管和第三晶体管。第三晶体管被配置为在第一和第二模式中选择性地导通和关断。描述其他实施例。

5. 发明申请

US20090295447A1 APPARATUS AND METHODS FOR A HIGH-VOLTAGE LATCH 有权
标题翻译：高压绞合装置及方法
公开(公告)号：US20090295447A1
公开(公告)日：2009-12-03
申请号：US12538766
申请日：2009-08-10
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356182 , G11C16/08 , G11C16/12
摘要： Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.
摘要翻译：一些实施例包括具有存储节点的设备和耦合到存储节点的锁存电路，以锁定在设备的第一模式和第二模式之一期间提供给存储节点的数据。锁存电路包括耦合在第一电压节点和第二电压节点之间的第一晶体管，第二晶体管和第三晶体管。第三晶体管被配置为在第一和第二模式中选择性地导通和关断。描述其他实施例。

6. 发明申请

US20080084767A1 APPARATUS FOR ELIMINATING LEAKAGE CURRENT OF A LOW Vt DEVICE IN A COLUMN LATCH 有权
标题翻译：用于消除柱塞中低Vt装置的泄漏电流的装置
公开(公告)号：US20080084767A1
公开(公告)日：2008-04-10
申请号：US11539564
申请日：2006-10-06
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： G11C7/10 , G11C16/06 , G11C11/00 , G11C11/34
CPC分类号： G11C7/1078 , G11C7/1087 , G11C16/12 , G11C2207/2227
摘要： An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.
摘要翻译：存储要写入非易失性存储器的存储单元的数据位的改进的CMOS高电压锁存器在待机操作模式和负载数据操作模式期间连接到Vdd电源电压。在高电压写入操作模式下，HV端子连接到高电压电源电压。交叉耦合高压CMOS锁存器连接在HV端子和接地端子之间，并具有锁存输入节点B和锁存输出节点A.输入缓冲器连接在HV端子和接地端子之间，并具有输入端子连接到DATA INPUT端子。输入缓冲器的输出端子连接到锁存器输入节点B.在负载数据操作模式期间，输入缓冲器被使能，以将数据从DATA INPUT端子加载到交叉耦合的高速缓存器的锁存器输入节点B，电压CMOS锁存器。

7. 发明授权

US07453725B2 Apparatus for eliminating leakage current of a low Vt device in a column latch 有权
标题翻译：用于消除列闩锁中的低Vt装置的泄漏电流的装置
公开(公告)号：US07453725B2
公开(公告)日：2008-11-18
申请号：US11539564
申请日：2006-10-06
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： G11C11/34 , G11C14/00 , G11C11/00 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C16/12 , G11C2207/2227
摘要： An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.
摘要翻译：存储要写入非易失性存储器的存储单元的数据位的改进的CMOS高电压锁存器在待机操作模式和负载数据操作模式期间连接到Vdd电源电压。在高电压写入操作模式下，HV端子连接到高电压电源电压。交叉耦合高压CMOS锁存器连接在HV端子和接地端子之间，并具有锁存输入节点B和锁存输出节点A.输入缓冲器连接在HV端子和接地端子之间，并具有输入端子连接到DATA INPUT端子。输入缓冲器的输出端子连接到锁存器输入节点B.在负载数据操作模式期间，输入缓冲器被使能，以将数据从DATA INPUT端子加载到交叉耦合的高速缓存器的锁存器输入节点B，电压CMOS锁存器。

8. 发明申请

US20080054973A1 LEAKAGE IMPROVEMENT FOR A HIGH-VOLTAGE LATCH 审中-公开
标题翻译：高压绞线的泄漏改进
公开(公告)号：US20080054973A1
公开(公告)日：2008-03-06
申请号：US11470536
申请日：2006-09-06
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： H03K3/356
CPC分类号： H03K3/356182 , G11C16/08 , G11C16/12
摘要： An improved CMOS high-voltage latch stores data bits to be written to memory cells of a non-volatile memory has two cross-coupled CMOS inverters. One of the inverters has a pull-down leg that includes a pass-gate high-voltage NMOS transistor that is connected between a latch output node and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to ground. A gate of the pass-gate high-voltage NMOS transistor receives a standby signal with a logic HIGH value of at most Vdd to turn on the pass-gate high-voltage NMOS transistor when the high-voltage CMOS latch is in a voltage mode of operation and during a high-voltage write mode of operation. The pass-gate high-voltage NMOS transistor thereby limits the voltage across the second high-voltage, low-threshold NMOS pull-down transistor to less than the standby signal in order to reduce punch-trough current and drain-to-substrate leakage of the second high-voltage, low-threshold NMOS pull-down transistor.
摘要翻译：改进的CMOS高电压锁存器存储要写入非易失性存储器的存储单元的数据位具有两个交叉耦合的CMOS反相器。其中一个逆变器具有一个下拉支路，其中包括一个连接在锁存输出节点和连接到地的第二个高电压，低阈值NMOS下拉晶体管之间的通过栅极的高压NMOS晶体管。栅极高压NMOS晶体管的栅极接收逻辑高电平至多为Vdd的待机信号，以在高电压CMOS锁存器处于电压模式在高电压写操作模式下操作。通过栅极高电压NMOS晶体管，将第二高电压，低阈值NMOS下拉晶体管的电压限制为小于备用信号，以便减少穿通电流和漏极到衬底泄漏第二个高电压，低阈值的NMOS下拉晶体管。

9. 发明授权

US07295046B2 Power down detection circuit 有权
标题翻译：断电检测电路
公开(公告)号：US07295046B2
公开(公告)日：2007-11-13
申请号：US11327990
申请日：2006-01-09
申请人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
发明人： Johnny Chan , Jeffrey Ming-Hung Tsai , Tin-Wai Wong
IPC分类号： H03K5/22
CPC分类号： G06F1/28 , H03K17/223 , H03K17/74
摘要： A power down reset circuit for asserting a signal when a first VDD voltage falls below a voltage threshold. The circuit has at least one diode coupled to the first VDD voltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first VDD voltage drops below a threshold level. The voltage detector is powered by the second voltage and is coupled to the at least one diode.
摘要翻译：一种用于在第一V DD电压下降到低于电压阈值时断定信号的掉电复位电路。电路具有耦合到第一V DD电压的至少一个二极管。所述至少一个二极管被配置为产生第二电压。至少一个电容器耦合到至少一个二极管以保持第二电压。当第一V DD电压下降到阈值以下时，电压检测器断言信号。电压检测器由第二电压供电并耦合到至少一个二极管。

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