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1. 发明授权

US07439556B2 Substrate driven field-effect transistor 有权
标题翻译：基板驱动场效应晶体管
公开(公告)号：US07439556B2
公开(公告)日：2008-10-21
申请号：US11093592
申请日：2005-03-29
申请人： Berinder P. S. Brar , Peter M. Asbeck
发明人： Berinder P. S. Brar , Peter M. Asbeck
IPC分类号： H01L31/0328
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/4175 , H01L29/42316
摘要： A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.
摘要翻译：衬底驱动场效应晶体管（FET）及其形成方法。在一个实施例中，衬底驱动FET包括具有覆盖其底表面的大部分的源极接触的衬底和在衬底上方的横向沟道。衬底驱动FET还包括在侧向通道上方的漏极接触。衬底驱动FET还包括将横向通道连接到衬底的源极互连，其可操作以在源极接触和侧向通道之间提供低电阻耦合。

2. 发明授权

US5185274A Self-aligned, self-passivated advanced dual lift-off heterojunction bipolar transistor method 失效
标题翻译：自对准，自钝化高级双提升异质结双极晶体管方法
公开(公告)号：US5185274A
公开(公告)日：1993-02-09
申请号：US746259
申请日：1991-08-15
申请人： Mau C. F. Chang , Peter M. Asbeck
发明人： Mau C. F. Chang , Peter M. Asbeck
IPC分类号： H01L21/28 , H01L21/318 , H01L21/331 , H01L29/737
CPC分类号： H01L29/66318 , H01L21/28 , H01L21/3185 , H01L29/7371
摘要： Heterojunction bipolar transistor is formed by using a common photoresist mask for self-aligning all critical dimensions including emitter and emitter contact to base contact to proton damaged collector regions beneath base contact and to passivate emitter periphery at same time.
摘要翻译：异质结双极晶体管通过使用公共光致抗蚀剂掩模形成，用于自动对准所有关键尺寸，包括发射极和发射极接触到基极接触处的质子损坏的集电极区域，同时钝化发射极外围。

3. 发明授权

US4996165A Self-aligned dielectric assisted planarization process 失效
标题翻译：自对准介质辅助平面化工艺
公开(公告)号：US4996165A
公开(公告)日：1991-02-26
申请号：US341464
申请日：1989-04-21
申请人： Mau-Chung F. Chang , Peter M. Asbeck
发明人： Mau-Chung F. Chang , Peter M. Asbeck
IPC分类号： H01L21/28 , H01L21/331 , H01L21/768
CPC分类号： H01L29/66318 , H01L21/28 , H01L21/76819 , Y10S148/043 , Y10S148/072 , Y10S148/075
摘要： A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure. In addition, intermediate etching steps may be employed for defining one or more transistor base or collector locations and metal or alloys deposited therein. Height variations in the resulting planar surface are controllable to within a fraction of a micron or less.
摘要翻译：使用诸如用于形成异质结或互连金属的半导体材料形式的升高特征来平坦化多层半导体结构中的表面的方法。形成特征的过程包括将残留光致抗蚀剂留在特征上。在特征形成和晶体管或其他结构位置的定义之后，电介质材料跨结构沉积。其余的光致抗蚀剂随后与其上沉积的电介质一起去除，留下特征之间的电介质。一层聚酰亚胺在结构上旋转并且在电介质和特征之间形成凹陷。通常重复材料沉积，蚀刻，电介质回填和旋涂步骤，直到在期望的多层结构中形成预定数量的接触或导电区域或互连金属层。此外，中间蚀刻步骤可以用于限定一个或多个晶体管基极或集电极位置以及沉积在其中的金属或合金。所得平面表面的高度变化可控制在微米或更小的分数之内。

4. 发明授权

US4731340A Dual lift-off self aligning process for making heterojunction bipolar transistors 失效
标题翻译：用于制造异质结双极晶体管的双重剥离自对准工艺
公开(公告)号：US4731340A
公开(公告)日：1988-03-15
申请号：US17957
申请日：1987-02-24
申请人： Mau-Chung F. Chang , Peter M. Asbeck
发明人： Mau-Chung F. Chang , Peter M. Asbeck
IPC分类号： H01L21/027 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L21/0272 , H01L29/0649 , H01L29/0821 , H01L29/7371 , Y10S438/951
摘要： A dual lift-off technique is used to provide self-alignment of the emitter area, the emitter contact, and the base contact of a heterojunction, bipolar transistor. A photoresist pattern which defines an emitter adjacent a base contact is formed on a suitable heterojunction bipolar semiconductor wafer. A base contact is formed by etching through the first semiconductor to the heterojunction and depositing metal on the second semiconductor. Dielectric is then deposited on the base contact. The photoresist is then lifted off with its dual covering of dielectric and metal. The emitter contact metal can then be deposited without requiring critical alignment because the base contact is covered with dielectric.
摘要翻译：双重剥离技术用于提供异质结双极晶体管的发射极区域，发射极接触和基极接触的自对准。在合适的异质结双极半导体晶片上形成限定邻近基极触点的发射极的光致抗蚀剂图案。通过将第一半导体蚀刻到异质结并在第二半导体上沉积金属形成基极接触。然后将电介质沉积在基底触点上。然后用其电介质和金属的双重覆盖物剥离光致抗蚀剂。然后可以沉积发射极接触金属，而不需要进行临界对准，因为基极接触被电介质覆盖。

5. 发明授权

US5311158A High power tuning device using layered varactors 失效
标题翻译：使用分层变容二极管的大功率调谐装置
公开(公告)号：US5311158A
公开(公告)日：1994-05-10
申请号：US911551
申请日：1992-07-09
申请人： Peter M. Asbeck , Richard C. Edwards , Garth D. Hammond , Dale W. Penner
发明人： Peter M. Asbeck , Richard C. Edwards , Garth D. Hammond , Dale W. Penner
IPC分类号： H03H7/00
CPC分类号： H03H7/00
摘要： A variety of embodiments of varactor diodes are disclosed ranging from an N.times.N matrix assembly of individually packaged diodes arranged in N rows and columns to a multi-continuous layered varactor. The matrix assembly varactor has N rows of discrete devices electrically coupled in parallel and multiple rows vertically aligned and electrically coupled in series to each other. The overall matrix assembly capacitance equals the individual diode capacitance of such assembly. When used as a tuning component across a tank coil transmission line, the RF voltage across any device in the matrix assembly is equal to the tank voltage divided by N.
摘要翻译：公开了变容二极管的各种实施例，其范围从N行和列排列成单独封装二极管的N×N矩阵组合到多连续分层变容二极管。矩阵组装变容二极管具有并行电耦合的N行离散器件，并且多行垂直对准并且彼此串联电耦合。整个矩阵组装电容等于这种组件的单独的二极管电容。当用作在箱式线圈传输线路上的调谐组件时，矩阵组件中的任何设备的RF电压等于槽电压除以N.

6. 发明授权

US5266819A Self-aligned gallium arsenide/aluminum gallium arsenide collector-up heterojunction bipolar transistors capable of microwave applications and method 失效
标题翻译：能够进行微波应用和方法的自对准砷化镓/砷化铝镓集电极异质结双极晶体管
公开(公告)号：US5266819A
公开(公告)日：1993-11-30
申请号：US700367
申请日：1991-05-13
申请人： Mau Chung F. Chang , Peter M. Asbeck
发明人： Mau Chung F. Chang , Peter M. Asbeck
IPC分类号： H01L21/306 , H01L21/331 , H01L29/737 , H01L29/72
CPC分类号： H01L29/66318 , H01L21/30621 , H01L29/7371
摘要： A C-up HBT is made to operate in the microwave/millimeter frequency range by self-aligning the collector uprisers on the base relative to proton damaged emitter regions and the base contacts which minimizes carrier injection into the extrinsic base. The use of about 7-10% indium in the indium gallium arsenide base is sufficient to stop the FREON-12 etch at the base after totally etching through the collector and single self-aligning mask.
摘要翻译： C-up HBT通过在底座上相对于质子损坏的发射极区域和基极触点自动对准收集器起动器而在微波/毫米频率范围内工作，这最小化载流子注入到外部基极中。在砷化铟镓基体中使用大约7-10％的铟足以在完全蚀刻通过集电体和单个自对准掩模之后停止基底处的FREON-12蚀刻。

7. 发明授权

US5028549A Etched back edge isolation process for heterojunction bipolar transistors 失效
标题翻译：用于异质结双极晶体管的蚀刻后缘隔离工艺
公开(公告)号：US5028549A
公开(公告)日：1991-07-02
申请号：US335477
申请日：1989-04-10
申请人： Mau-Chung F. Chang , Peter M. Asbeck
发明人： Mau-Chung F. Chang , Peter M. Asbeck
IPC分类号： H01L21/76
CPC分类号： H01L21/7605 , Y10S148/01 , Y10S148/10 , Y10S148/103
摘要： A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.
摘要翻译：在晶片上隔离单个异质结双极晶体管（HBT）的方法增加了当使用质子注入来隔离晶体管时可获得的电流增益。在蚀刻封盖层时，用于在隔离注入期间覆盖晶体管位置的光致抗蚀剂图案被切割。然后将电介质沉积在蚀刻的表面上，包括底切部分。剥离光致抗蚀剂，并且在未被电介质覆盖的区域中的晶片上制造HBT。底切部分上的电介质将发射极电流限制在与隔离植入物略微移开的区域，并提供改善的电流增益。

8. 发明授权

US08159295B2 Supply-modulated RF power amplifier and RF amplification methods 有权
标题翻译：供应调制RF功率放大器和RF放大方法
公开(公告)号：US08159295B2
公开(公告)日：2012-04-17
申请号：US12785090
申请日：2010-05-21
申请人： Peter M. Asbeck , Donald Kimball , Jinseong Jeong
发明人： Peter M. Asbeck , Donald Kimball , Jinseong Jeong
IPC分类号： H03G3/20 , H03F3/04
CPC分类号： H03F1/0216 , H03F1/3247 , H03F3/189 , H03F3/24 , H03F2200/207 , H03F2200/451 , H03F2201/3233
摘要： An embodiment of the invention is a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and added back into the filtered envelope signal. An iterative process of the rectifying, low pass filtering the residue signal adding it back is continued until a condition of VDD(t)≧Venv(t) is met. Another embodiment provides a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and multiplied by a first constant that is greater than one, and then added back into the filtered envelope signal. A second constant is added into the filtered envelope signal so that the condition VDD(t)≧Venv(t) is met.
摘要翻译：本发明的一个实施例是产生用于RF放大器的电源调制器的减小带宽包络信号VDD（t）的方法。 RF放大器输入Venv（t）的包络信号被低通滤波。从包络信号中减去经滤波的包络信号以获得差分信号，该信号被整流以产生残留信号。残留信号被低通滤波并加到滤波后的包络信号中。对残留信号进行整流，低通滤波的迭代过程继续进行，直到满足VDD（t）≥Venv（t）的条件为止。另一实施例提供了一种为RF放大器的电源调制器生成减小带宽包络信号VDD（t）的方法。 RF放大器输入Venv（t）的包络信号被低通滤波。从包络信号中减去经滤波的包络信号以获得差分信号，该信号被整流以产生残留信号。残差信号被低通滤波并乘以大于1的第一常数，然后加到滤波的包络信号中。第二常数被加到滤波的包络信号中，使得满足条件VDD（t）≥Venv（t）。

9. 发明申请

US20100295613A1 SUPPLY-MODULATED RF POWER AMPLIFIER AND RF AMPLIFICATION METHODS 有权
标题翻译：供应调制射频功率放大器和射频放大方法
公开(公告)号：US20100295613A1
公开(公告)日：2010-11-25
申请号：US12785090
申请日：2010-05-21
申请人： Peter M. Asbeck , Donald Kimball , Jinseong Jeong
发明人： Peter M. Asbeck , Donald Kimball , Jinseong Jeong
IPC分类号： H03F1/26
CPC分类号： H03F1/0216 , H03F1/3247 , H03F3/189 , H03F3/24 , H03F2200/207 , H03F2200/451 , H03F2201/3233
摘要： An embodiment of the invention is a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and added back into the filtered envelope signal. An iterative process of the rectifying, low pass filtering the residue signal adding it back is continued until a condition of VDD(t)≧Venv(t) is met. Another embodiment provides a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and multiplied by a first constant that is greater than one, and then added back into the filtered envelope signal. A second constant is added into the filtered envelope signal so that the condition VDD(t)≧Venv(t) is met.
摘要翻译：本发明的一个实施例是产生用于RF放大器的电源调制器的减小带宽包络信号VDD（t）的方法。 RF放大器输入Venv（t）的包络信号被低通滤波。从包络信号中减去经滤波的包络信号以获得差分信号，该信号被整流以产生残留信号。残留信号被低通滤波并加到滤波后的包络信号中。对残留信号进行整流，低通滤波的迭代过程继续进行，直到满足VDD（t）≥Venv（t）的条件为止。另一实施例提供了一种为RF放大器的电源调制器生成减小带宽包络信号VDD（t）的方法。 RF放大器输入Venv（t）的包络信号被低通滤波。从包络信号中减去经滤波的包络信号以获得差分信号，该信号被整流以产生残留信号。残差信号被低通滤波并乘以大于1的第一常数，然后加到滤波的包络信号中。第二常数被加到滤波的包络信号中，使得满足条件VDD（t）≥Venv（t）。

10. 发明授权

US06674103B2 HBT with nitrogen-containing current blocking base collector interface and method for current blocking 有权
标题翻译： HBT与含氮电流阻塞基极收集器接口和电流阻塞方法
公开(公告)号：US06674103B2
公开(公告)日：2004-01-06
申请号：US09919367
申请日：2001-07-31
申请人： Charles W. Tu , Peter M. Asbeck , Kazuhiro Mochizuki , Rebecca Welty
发明人： Charles W. Tu , Peter M. Asbeck , Kazuhiro Mochizuki , Rebecca Welty
IPC分类号： H01L310328
CPC分类号： H01L29/7371 , H01L29/0821 , H01L29/1004 , H01L29/2003
摘要： An improved HBT of the invention reduces the current blocking effect at the base-collector interface. Nitrogen is incorporated at the base-collector interface in an amount sufficient to reduce the conduction band energy of the collector at the base-collector interface to equal the conduction band energy of the base. In a preferred embodiment, a nitrogen concentration on the order of 2% is used in a thin ˜20 nm layer at the base-collector interface. Preferred embodiment HBTs of the invention include both GaAs HBTs and InP transistors in various layer structures, e.g., single and double heterojunction bipolar transistors and blocked hole bipolar transistors.
摘要翻译：本发明的改进的HBT降低了基极 - 集电极界面处的电流阻塞效应。在基极 - 集电极界面处以足以降低集电极界面处的集电极的导带能量等于基极的导带能量的量引入氮。在优选的实施方案中，在基极 - 收集器界面处的薄的〜20nm层中使用2％量级的氮浓度。本发明的优选实施例HBT包括GaAs HBT和各种层结构中的InP晶体管，例如单和双异质结双极晶体管和阻塞双极晶体管。

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