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1. 发明授权

US07439556B2 Substrate driven field-effect transistor 有权
标题翻译：基板驱动场效应晶体管
公开(公告)号：US07439556B2
公开(公告)日：2008-10-21
申请号：US11093592
申请日：2005-03-29
申请人： Berinder P. S. Brar , Peter M. Asbeck
发明人： Berinder P. S. Brar , Peter M. Asbeck
IPC分类号： H01L31/0328
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/4175 , H01L29/42316
摘要： A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.
摘要翻译：衬底驱动场效应晶体管（FET）及其形成方法。在一个实施例中，衬底驱动FET包括具有覆盖其底表面的大部分的源极接触的衬底和在衬底上方的横向沟道。衬底驱动FET还包括在侧向通道上方的漏极接触。衬底驱动FET还包括将横向通道连接到衬底的源极互连，其可操作以在源极接触和侧向通道之间提供低电阻耦合。

2. 发明授权

US08415737B2 Semiconductor device with a pillar region and method of forming the same 有权
标题翻译：具有柱区域的半导体器件及其形成方法
公开(公告)号：US08415737B2
公开(公告)日：2013-04-09
申请号：US11765252
申请日：2007-06-19
申请人： Berinder P. S. Brar , Wonill Ha
发明人： Berinder P. S. Brar , Wonill Ha
IPC分类号： H01L29/76
CPC分类号： H01L21/823487 , H01L29/66848 , H01L29/8122 , H01L29/872
摘要： A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.
摘要翻译：半导体器件，其形成方法以及包括半导体器件的功率转换器。在一个实施例中，半导体器件包括重掺杂衬底，重掺杂衬底下面的源极/漏极接触以及重掺杂衬底之上的沟道层。半导体器件还包括在沟道层上方的重掺杂源极/漏极层以及重掺杂源极/漏极层上方的另一个源极/漏极接触。该半导体器件还包括通过另一个源/漏接触，重掺杂源/漏层和沟道层的部分的柱区域，以在其间形成垂直单元。半导体器件的非导电区域位于沟道层的部分中。半导体器件还包括在柱状区域中的非导电区域之上的栅极。半导体器件还可以包括包括沟道层和肖特基接触的肖特基二极管。

3. 发明授权

US08043910B2 Integrated semiconductor structure including a heterojunction bipolar transistor and a Schottky diode 有权
标题翻译：包括异质结双极晶体管和肖特基二极管的集成半导体结构
公开(公告)号：US08043910B2
公开(公告)日：2011-10-25
申请号：US12789498
申请日：2010-05-28
申请人： Berinder P. S. Brar
发明人： Berinder P. S. Brar
IPC分类号： H01L21/8249
CPC分类号： H01L29/7371 , H01L27/0605 , H01L29/872
摘要： An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
摘要翻译：集成半导体结构包括异质结双极晶体管和肖特基二极管。所述结构具有衬底，所述异质结双极晶体管覆盖并接触所述衬底，其中所述异质结双极晶体管包括晶体管集电极层和覆盖所述衬底并叠加在所述晶体管集电极层上的肖特基二极管。肖特基二极管包括肖特基二极管阻挡层结构，其期望不是与晶体管集电极层相同的材料，掺杂和厚度。

4. 发明授权

US07563713B2 Semiconductor devices having plated contacts, and methods of manufacturing the same 有权
标题翻译：具有电镀触点的半导体器件及其制造方法
公开(公告)号：US07563713B2
公开(公告)日：2009-07-21
申请号：US11064535
申请日：2005-02-23
申请人： Petra V. Rowell , Miguel E. Urteaga , Richard L. Pierson, Jr. , Berinder P. S. Brar
发明人： Petra V. Rowell , Miguel E. Urteaga , Richard L. Pierson, Jr. , Berinder P. S. Brar
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76879
摘要： A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening, for example by plating, to form a first contact on the surface or seed layer. The mask and the top layer of the semiconductor structure, except for the portion under the first contact, are removed to expose a second layer of the semiconductor structure. An insulating layer is formed along the sidewalls of the first contact and the top layer of the semiconductor structure beneath the first contact. A mask is then applied to the second layer and a second contact is formed by selectively depositing metal only on the portion of the second layer exposed by the opening.
摘要翻译：将掩模层施加到沉积在表面上的半导体结构或种子层的表面。掩模层具有暴露一部分表面或种子层的具有高纵横比的亚微米宽度开口。导电材料例如通过电镀与开口一致，以在表面或种子层上形成第一接触。半导体结构的掩模和顶层除了第一接触部分之外，被除去以露出半导体结构的第二层。沿着第一接触的侧壁和第一接触下方的半导体结构的顶层形成绝缘层。然后将掩模施加到第二层，并且通过仅将金属选择性地沉积在由开口暴露的第二层的部分上来形成第二接触。

5. 发明授权

US07354820B2 Heterojunction bipolar transistor with dielectric assisted planarized contacts and method for fabricating 有权
标题翻译：具有介质辅助平面化触点的异质结双极晶体管及其制造方法
公开(公告)号：US07354820B2
公开(公告)日：2008-04-08
申请号：US11227858
申请日：2005-09-14
申请人： Richard L. Pierson, Jr. , James Chingwei Li , Berinder P. S. Brar , John A. Higgins
发明人： Richard L. Pierson, Jr. , James Chingwei Li , Berinder P. S. Brar , John A. Higgins
IPC分类号： H01L21/8249
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S438/978
摘要： A method for fabricating an HBT is disclosed, wherein successive emitter, base, collector and sub-collector epitaxial layers are deposited on a substrate, with the substrate being adjacent to the sub-collector layer. The epitaxial layers are etched to provide locations for contact metals and emitter, base and contact metals are deposited on the emitter, base and sub-collector epitaxial layers, respectively. A self-alignment material is deposited on the surface of the substrate around the epitaxial layers and a planarization material is deposited on and covers the top surface of the HBT. The planarization material is then etched so it has a planar surface about the same level as the surface of the self-alignment material and the contact metals protrude from the planar surface. The planar metals are then deposited over the protruding portions of the contact metals.
摘要翻译：公开了一种用于制造HBT的方法，其中连续的发射极，基极，集电极和次集电极外延层沉积在衬底上，衬底与子集电极层相邻。外延层被蚀刻以提供用于接触金属和发射极的位置，基极和接触金属分别沉积在发射极，基极和次集电极外延层上。自对准材料沉积在外延层周围的衬底表面上，平坦化材料沉积在HBT的顶表面上并覆盖其上表面。然后对平坦化材料进行蚀刻，使其具有与自对准材料的表面大致相同的平面，并且接触金属从平坦表面突出。然后将平面金属沉积在接触金属的突出部分上。

6. 发明授权

US07030038B1 Low temperature method for forming a thin, uniform oxide 有权
标题翻译：低温法形成薄均匀的氧化物
公开(公告)号：US07030038B1
公开(公告)日：2006-04-18
申请号：US09176422
申请日：1998-10-21
申请人： Glen D. Wilk , Robert M. Wallace , Berinder P. S. Brar
发明人： Glen D. Wilk , Robert M. Wallace , Berinder P. S. Brar
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31662 , H01L21/02238 , H01L21/02255 , H01L21/28211 , H01L29/51 , H01L29/7833
摘要： This invention pertains generally to forming thin oxides at low temperatures, and more particularly to forming uniformly thick, thin oxides. We disclose a low temperature method for forming a thin, uniform oxide 16 on a silicon surface 12. This method includes providing a partially completed integrated circuit on a semiconductor substrate 10 with a clean, hydrogen terminated or atomically flat, silicon surface 12; and stabilizing the substrate at a first temperature. The method further includes exposing the silicon surface to an atmosphere 14 including ozone, while maintaining the substrate 10 at the first temperature. In this method, the exposing step creates a uniformly thick, oxide film 16. This method is suitable for room temperature processing.
摘要翻译：本发明一般涉及在低温下形成薄氧化物，尤其涉及形成均匀的厚的氧化物。我们公开了在硅表面12上形成薄均匀氧化物16的低温方法。该方法包括在半导体衬底10上提供部分完成的集成电路，其具有清洁的氢封端或原子平坦的硅表面12; 以及在第一温度下稳定所述衬底。该方法还包括将硅表面暴露于包括臭氧的气氛14，同时将衬底10保持在第一温度。在该方法中，曝光步骤产生均匀厚的氧化膜16。该方法适用于室温处理。

7. 发明授权

US07675090B2 Semiconductor device having a contact on a buffer layer thereof and method of forming the same 有权
标题翻译：在其缓冲层上具有接触的半导体器件及其形成方法
公开(公告)号：US07675090B2
公开(公告)日：2010-03-09
申请号：US11732301
申请日：2007-04-03
申请人： Mariam Gergi Sadaka , Berinder P. S. Brar , Wonill Ha , Chanh Ngoc Minh Nguyen
发明人： Mariam Gergi Sadaka , Berinder P. S. Brar , Wonill Ha , Chanh Ngoc Minh Nguyen
IPC分类号： H01L31/0328
CPC分类号： H01L29/1029 , H01L21/6835 , H01L29/1083 , H01L29/4175 , H01L29/41766 , H01L29/66462 , H01L29/7783 , H01L29/7785 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381
摘要： A semiconductor device and method of forming the same. The semiconductor device includes an epitaxially grown and conductive buffer layer having a contact covering a substantial portion of a bottom surface thereof and a lateral channel above the buffer layer. The semiconductor device also includes another contact above the lateral channel and an interconnect that connects the lateral channel to the buffer layer, operable to provide a low resistance coupling between the contact and the lateral channel.
摘要翻译：一种半导体器件及其制造方法。半导体器件包括外延生长和导电缓冲层，其具有覆盖其底表面的大部分的接触和缓冲层上方的横向通道。半导体器件还包括在横向通道上方的另一接触件和将横向通道连接到缓冲层的互连件，可操作以在触头和横向通道之间提供低电阻耦合。

8. 发明申请

US20070298564A1 Vertical Field-Effect Transistor and Method of Forming the Same 有权
公开(公告)号：US20070298564A1
公开(公告)日：2007-12-27
申请号：US11765323
申请日：2007-06-19
申请人： Berinder P. S. Brar , Wonill Ha
发明人： Berinder P. S. Brar , Wonill Ha
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L29/872
摘要： A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

9. 发明授权

US06815237B1 Testing apparatus and method for determining an etch bias associated with a semiconductor-processing step 失效
标题翻译：用于确定与半导体处理步骤相关联的蚀刻偏压的测试装置和方法
公开(公告)号：US06815237B1
公开(公告)日：2004-11-09
申请号：US10675680
申请日：2003-09-29
申请人： James Chingwei Li , Richard L. Pierson, Jr. , Berinder P. S. Brar
发明人： James Chingwei Li , Richard L. Pierson, Jr. , Berinder P. S. Brar
IPC分类号： H01L2166
CPC分类号： H01L22/34 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A testing apparatus for determining the etch bias associated with a semiconductor-processing step includes a substrate, a first cathode finger with a first width on the substrate, a second cathode finger with a second width on the substrate, and a cathode large area on the substrate wherein the cathode large area has a third width W″ and a length L″ that are both substantially larger than either of the first and second widths.
摘要翻译：用于确定与半导体处理步骤相关联的蚀刻偏压的测试装置包括：衬底，在衬底上具有第一宽度的第一阴极指状物，在衬底上具有第二宽度的第二阴极指状物，以及位于衬底上的阴极大面积衬底，其中阴极大面积具有大于第一宽度和第二宽度中的任一个的第三宽度W“和长度L”。

10. 发明授权

US06800531B2 Method of fabricating a bipolar transistor 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US06800531B2
公开(公告)日：2004-10-05
申请号：US10353208
申请日：2003-01-27
申请人： Richard L. Pierson, Jr. , James Chingwei Li , Berinder P. S. Brar , John A. Higgins
发明人： Richard L. Pierson, Jr. , James Chingwei Li , Berinder P. S. Brar , John A. Higgins
IPC分类号： H01L21331
CPC分类号： H01L29/66318 , H01L29/0821 , H01L29/7371
摘要： A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
摘要翻译：为InP子集电极之上的异质结双极晶体管（HBT）的集电极提供了一个薄的InGaAs接触层。接触层提供低电阻接触机构和高导热性路径，用于通过子集电器去除器件热，并且还用作在器件制造期间保护子集电极的蚀刻停止。在HBT的其余部分横向的子集电极的一部分被优选地通过离子注入电绝缘，以提供器件的电隔离，并通过避免通过子集电极的蚀刻来改善其平面度。

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