专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07284215B1 Method to solve similar timing paths 有权
标题翻译：解决类似时序路径的方法
公开(公告)号：US07284215B1
公开(公告)日：2007-10-16
申请号：US10798046
申请日：2004-03-11
申请人： Von-Kyoung Kim , Dakshesh Amin , Sriram Satakopan , Peter F. Lai
发明人： Von-Kyoung Kim , Dakshesh Amin , Sriram Satakopan , Peter F. Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the number of unique critical timing path patterns for analysis. In some embodiments of the present invention a method for use in connection with an integrated circuit design includes identifying distinct timing paths of the integrated circuit design. The distinct timing paths have timing violations. The method includes associating a first plurality of the distinct timing paths with a first set of timing paths. Individual ones of the first plurality belonging to a second set of timing paths and include a first common characteristic. The method includes improving the first set of timing paths based at least in part on an improvement to an individual timing path of the first set of timing paths.
摘要翻译：已经发现了用于改进表现出相似特征的多个关键时序路径的技术。该技术通过减少用于分析的唯一关键时序路径模式的数量来有效地改善多个关键定时路径。在本发明的一些实施例中，结合集成电路设计使用的方法包括识别集成电路设计的不同的定时路径。不同的定时路径具有定时违规。该方法包括将第一多个不同的定时路径与第一组定时路径相关联。属于第二组定时路径的第一个复数个体中的各个包括第一共同特性。该方法包括至少部分地基于对第一组定时路径的单个定时路径的改进来改进第一组定时路径。

2. 发明授权

US06654942B2 Method and system for providing a netlist driven integrated router in a non-netlist driven environment 有权
公开(公告)号：US06654942B2
公开(公告)日：2003-11-25
申请号：US09938120
申请日：2001-08-22
申请人： Sachin Chopra , Peter Fu , Kong-Fal Woo , Peter Lai , Srirarm Satakopan , Hsiu-Nien Chen , Von-Kyoung Kim , Yongjun Zhang
发明人： Sachin Chopra , Peter Fu , Kong-Fal Woo , Peter Lai , Srirarm Satakopan , Hsiu-Nien Chen , Von-Kyoung Kim , Yongjun Zhang
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

3. 发明授权

US07032200B1 Low threshold voltage transistor displacement in a semiconductor device 有权
标题翻译：半导体器件中的低阈值电压晶体管位移
公开(公告)号：US07032200B1
公开(公告)日：2006-04-18
申请号：US10657964
申请日：2003-09-09
申请人： Sriram Satakopan , Arvindvel Shanmugavel , Shunjiang Xu , Von-Kyoung Kim , Peter Lai
发明人： Sriram Satakopan , Arvindvel Shanmugavel , Shunjiang Xu , Von-Kyoung Kim , Peter Lai
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A technique improves the performance of an integrated circuit design by selectively replacing low Vt transistors with standard Vt transistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vt variant of a gate instance increases a path cycle time as compared to a standard Vt counterpart, the maximum of the path cycle times for all paths that include the low Vt variant and the maximum of the path cycle time for these paths with a standard Vt variant are calculated. If the maximum path cycle time for the path including the low Vt variant is greater than the maximum path cycle time for the path including the standard Vt variant, then that low Vt variant is substituted with a standard Vt variant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.
摘要翻译：一种技术通过用标准的V FET晶体管选择性地替代低V 2晶体管来改善集成电路设计的性能。用于替换的门的选择可以基于多路径时序分析。如果栅极实例的低V 0变量与标准VTA对应物相比增加了路径周期时间，则包括所有路径的路径周期时间的最大值计算出具有标准V变量的这些路径的低V L变量和路径周期时间的最大值。如果包含低V OUT变量的路径的最大路径周期时间大于包括标准V变量的路径的最大路径周期时间，则该低 V 变体用标准VTA变体代替。因此，根据本发明制备的集成电路设计可以表现出改善的循环时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式