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1. 发明授权

US5900749A Threshold voltage level generator for time division duplex communications 失效
标题翻译：用于时分双工通信的阈值电压电平发生器
公开(公告)号：US5900749A
公开(公告)日：1999-05-04
申请号：US856358
申请日：1997-05-14
申请人： Alan F. Hendrickson , Peter E. Sheldon
发明人： Alan F. Hendrickson , Peter E. Sheldon
IPC分类号： H03K5/08 , H04L25/06 , H03K5/00 , H03K25/06
CPC分类号： H04L25/065 , H03K5/082 , H04L25/062
摘要： A circuit for generating a threshold voltage level from a time division duplex analog data signal. The circuit comprises a sample/hold circuit and an amplifier. The sample/hold circuit is arranged to sample the threshold voltage level during a reception interval and hold the threshold voltage level during a transmission interval. The amplifier includes an operational amplifier coupled to the sample/hold circuit for amplifying the analog data signal during a reception interval and amplifying the threshold voltage level during a transmission interval. A transconductance device is coupled to the operational amplifier, and a plurality of load legs are respectively coupled to a plurality of bias legs. A first selected pair of the respectively coupled load legs and bias legs is coupled to the transconductance device, and a second selected pair of the respectively coupled load legs and bias legs coupled to the output of the amplifier to provide the threshold voltage level.
摘要翻译：一种用于从时分双工模拟数据信号产生阈值电压电平的电路。电路包括采样/保持电路和放大器。采样/保持电路被布置成在接收间隔期间对门限电压电平进行采样，并在发送间隔期间保持阈值电压电平。放大器包括耦合到采样/保持电路的运算放大器，用于在接收间隔期间放大模拟数据信号，并在发送间隔期间放大阈值电压电平。跨导装置耦合到运算放大器，并且多个负载支路分别耦合到多个偏置支路。分别耦合的负载支路和偏置支路的第一选择的一对耦合到跨导装置，以及耦合到放大器的输出端的分别耦合的负载支路和偏置支路的第二选定对，以提供阈值电压电平。

2. 发明申请

US20130314130A1 Frequency Synthesizer with Zero Deterministic Jitter 有权
标题翻译：具有零确定性抖动的频率合成器
公开(公告)号：US20130314130A1
公开(公告)日：2013-11-28
申请号：US13481038
申请日：2012-05-25
申请人： Xianyao Wang , Peter E. Sheldon , Christopher M. Green
发明人： Xianyao Wang , Peter E. Sheldon , Christopher M. Green
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , G06F1/022 , H03B2202/02
摘要： A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.
摘要翻译：频率合成器系统可以产生两个中间时钟信号，每个中间时钟信号具有相同的标称频率（fN），具有确定性抖动的相同周期模式和相同的相应平均频率（fA）。然而，一个中间时钟信号中的周期模式可以是相对于另一个中间时钟信号中的周期模式的异相的指定数量（N）个周期。在每个中间时钟信号中，循环模式可以每2N个循环重复。两个中间时钟信号中每一个周期的持续时间由fN和循环模式中的确定性抖动来定义。可以通过两（2）个中间时钟信号进行相位内插来产生输出时钟信号，并将得到的相位内插时钟信号除以N.由此产生的输出时钟信号具有与fA / N相当的精确频率，并且是空闲的的确定性抖动。

3. 发明授权

US6125139A Narrowband digital cordless telephone 失效
标题翻译：窄带数字无绳电话
公开(公告)号：US6125139A
公开(公告)日：2000-09-26
申请号：US760883
申请日：1996-12-06
申请人： Alan Hendrickson , Paul Schnizlein , Jacqueline Mullins , Peter E. Sheldon
发明人： Alan Hendrickson , Paul Schnizlein , Jacqueline Mullins , Peter E. Sheldon
IPC分类号： H04B7/26 , H04M11/06
CPC分类号： H04M1/725 , G06F2213/0038 , H04M1/60
摘要： A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives analog receive voice signals and transmits analog transmit voice signals. In addition, the unit transmits digital baseband transmit signals and receives digital formatted baseband receive signals. The unit includes a baseband chip, as well as an audio functions circuit and a system control functions circuit. The audio functions circuit comprises an audio front end for receiving the analog receive voice signals and transmitting the analog transmit voice signals, and an adaptive differential pulse code modulator codec, connected to the audio front end, for converting the analog receive voice signals to the digital transmit signals and converting the digital formatted baseband receive signals to the analog transmit voice signals. The system control functions circuit comprises a microcontroller, connected to the codec, for controlling the baseband chip, a memory accessible by the microcontroller for storing control instructions, an interrupt controller connected to the microcontroller, a parallel port connected to the interrupt controller, a wake-up timer connected to the interrupt controller, a clock generator connected to the microcontroller, and a synchronous serial port connected to the interrupt controller.
摘要翻译：公开了一种数字无绳电信单元，用于在与类似单元配对并与网络连接时用于通信。该单元接收模拟接收语音信号并传输模拟传输语音信号。此外，该单元发射数字基带发射信号并接收数字格式的基带接收信号。该单元包括基带芯片，以及音频功能电路和系统控制功能电路。音频功能电路包括用于接收模拟接收语音信号并发送模拟发送语音信号的音频前端，以及连接到音频前端的自适应差分脉冲编码调制器编解码器，用于将模拟接收语音信号转换成数字发送信号并将数字格式的基带接收信号转换成模拟发送语音信号。系统控制功能电路包括连接到编解码器的微控制器，用于控制基带芯片，由微控制器访问的用于存储控制指令的存储器，连接到微控制器的中断控制器，连接到中断控制器的并行端口，唤醒 - 连接到中断控制器的定时器，连接到微控制器的时钟发生器和连接到中断控制器的同步串行端口。

4. 发明授权

US4763022A TTL-to-CMOS buffer 失效
标题翻译： TTL到CMOS缓冲器
公开(公告)号：US4763022A
公开(公告)日：1988-08-09
申请号：US354
申请日：1987-01-05
申请人： Peter E. Sheldon
发明人： Peter E. Sheldon
IPC分类号： H03K19/003 , H03K19/017 , H03K19/0185 , H03K5/01 , H03K17/687
CPC分类号： H03K19/00384 , H03K19/01721 , H03K19/018521
摘要： A TTL-to-CMOS converter consists of a plurality of N-channel and P-channel MOS transistors, each of which is fabricated so as to have a predetermined channel Width-to-Length ratio (W/L). The transistors are arranged to include an input complementary pair for accepting TTL-level signals and an output complementary pair for providing CMOS-level signals. An N-channel tracking transistor is coupled between the drain electrodes of the P-channel and N-channel transistors of the input complementary pair. The (W/L) of the tracking transistor is approximately 1/8 to to 1/7 times the (W/L) of the N-channel transistor of the input complementary pair. This arrangement establishes a converter switch point with a significantly greater degree of accuracy than otherwise attainable. A pull-up transistor has a gate electrode coupled to the input terminal of the input complementary pair and a drain electrode coupled to the input electrode of the output complementary pair. The pull-up transistor operates to pull the input terminal of the output complementary pair toward Vdd as the TTL logic level at the input of the Buffer goes low.
摘要翻译： TTL至CMOS转换器由多个N沟道和P沟道MOS晶体管组成，每个N沟道和P沟道MOS晶体管的制造方式具有预定的沟道宽度比（W / L）。晶体管被布置成包括用于接收TTL电平信号的输入互补对和用于提供CMOS电平信号的输出互补对。 N沟道跟踪晶体管耦合在P沟道的漏极和输入互补对的N沟道晶体管之间。跟踪晶体管的（W / L）大约是输入互补对的N沟道晶体管的（W / L）的1/8至1/7倍。这种安排建立了一种转换器切换点，具有比其它可实现的显着更高的准确度。上拉晶体管具有耦合到输入互补对的输入端的栅电极和耦合到输出互补对的输入电极的漏电极。当缓冲器输入端的TTL逻辑电平变为低电平时，上拉晶体管工作，将输出互补对的输入端子向Vdd拉。

5. 发明授权

US08575973B1 Frequency synthesizer with zero deterministic jitter 有权
标题翻译：具有零确定性抖动的频率合成器
公开(公告)号：US08575973B1
公开(公告)日：2013-11-05
申请号：US13481038
申请日：2012-05-25
申请人： Xianyao Wang , Peter E. Sheldon , Christopher M. Green
发明人： Xianyao Wang , Peter E. Sheldon , Christopher M. Green
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , G06F1/022 , H03B2202/02
摘要： A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.
摘要翻译：频率合成器系统可以产生两个中间时钟信号，每个中间时钟信号具有相同的标称频率（fN），具有确定性抖动的相同周期模式和相同的相应平均频率（fA）。然而，一个中间时钟信号中的周期模式可以是相对于另一个中间时钟信号中的周期模式的异相的指定数量（N）个周期。在每个中间时钟信号中，循环模式可以每2N个循环重复。两个中间时钟信号中每一个周期的持续时间由fN和循环模式中的确定性抖动来定义。可以通过两（2）个中间时钟信号进行相位内插来产生输出时钟信号，并将得到的相位内插时钟信号除以N.由此产生的输出时钟信号具有与fA / N相当的精确频率，并且是空闲的的确定性抖动。

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