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1. 发明授权

US4428040A Low power consumption electronic circuit 失效
标题翻译：低功耗电子电路
公开(公告)号：US4428040A
公开(公告)日：1984-01-24
申请号：US292584
申请日：1981-08-13
申请人： Osamu Yamashiro , Toyohiko Hongo
发明人： Osamu Yamashiro , Toyohiko Hongo
IPC分类号： G05F3/24 , G04C10/00 , G04G19/00 , G04G19/02 , H02M3/07 , H02M3/06
CPC分类号： G04G19/02 , G04G19/00 , H02M3/07
摘要： According to the present invention, the voltage of a battery is supplied to an electronic circuit such as a watch circuit through a step down circuit which is constructed of capacitors and switching MIDFETs. The step down circuit performs a current converting operation as well as a voltage converting operation. The operating current of the electronic circuit is reduced by the reduction in the operating voltage of the same. As a result that the operating current level of the electronic circuit is dropped and that the current conversion is performed by the step down circuit, the battery current is relatively largely dropped. The construction thus far described elongates the lifetime of the battery. According to the present invention, therefore, there is provided a circuit which is proper for driving the step down circuit.
摘要翻译：根据本发明，通过由电容器和开关式MIDFET构成的降压电路将电池的电压提供给诸如钟表电路的电子电路。降压电路执行电流转换操作以及电压转换操作。电子电路的工作电流由于其工作电压的降低而降低。结果，电子电路的工作电流水平下降，并且通过降压电路执行电流转换，电池电流相对较大地下降。迄今为止描述的结构延长了电池的寿命。因此，根据本发明，提供了适于驱动降压电路的电路。

2. 发明授权

US4309665A Complementary amplifier circuit 失效
标题翻译：互补放大器电路
公开(公告)号：US4309665A
公开(公告)日：1982-01-05
申请号：US119510
申请日：1980-02-07
申请人： Osamu Yamashiro
发明人： Osamu Yamashiro
IPC分类号： G04F5/06 , H03B5/36 , H03F3/16 , H03F3/18 , H03F3/30 , H03F3/34 , H03F3/345 , H03F3/185
CPC分类号： H03F3/3001 , G04F5/06 , H03B5/364 , H03F3/16
摘要： A complementary amplifier circuit includes a p-channel MISFET and an n-channel MIS connected in series. The gate of the p-channel FET transistor is D.C. biased by a high impedance resistor connected between the gate and drain electrodes, and the gate of the n-channel FET is D.C. biased by a current mirror circuit formed by another n-channel FET. This complementary amplifier circuit has the advantages that the operational lower limit voltage thereof is equal to the threshold voltage of one of the MOSFETs and that stabilized operation of the amplifier is easily obtained.
摘要翻译：互补放大器电路包括串联连接的p沟道MISFET和n沟道MIS。 p沟道FET晶体管的栅极由连接在栅极和漏极之间的高阻抗电阻器偏置，并且n沟道FET的栅极被由另一n沟道FET形成的电流镜像电路偏置。这种互补放大器电路具有其工作下限电压等于其中一个MOSFET的阈值电压的优点，并且容易获得放大器的稳定操作。

3. 发明授权

US4247826A Semiconductor integrated amplifier 失效
标题翻译：半导体集成放大器
公开(公告)号：US4247826A
公开(公告)日：1981-01-27
申请号：US902852
申请日：1978-05-04
申请人： Takeshi Gappa , Osamu Yamashiro
发明人： Takeshi Gappa , Osamu Yamashiro
IPC分类号： H01L21/822 , H01L27/04 , H01L27/07 , H01L27/08 , H01L27/092 , H01L29/94 , H03B5/36 , H03F3/16 , H03F3/34 , H03F3/345 , H03F3/185 , H03F3/187
CPC分类号： H01L29/94 , H01L27/0727 , H01L27/092 , H03B5/364 , H03F3/16
摘要： A semiconductor integrated amplifier having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of the MISFETs, a power source to which the MISFETs are connected in series, and a DC current blocking capacitor through which the gates of the MISFETs are connected to each other. The amplifier has a gate capacitance one terminal of which is constituted by a well formed in the substrate and connected to high voltage side of power supply, while the other electrode thereof is constituted by a gate electrode formed on the well and connected to the low voltage side of the power supply. Parasitic capacitance of the capacitor is considerably reduced to allow a wider range of frequency adjustment of the amplifier.
摘要翻译：集成在单个半导体衬底中的具有p沟道型MISFET和n沟道型MISFET的半导体集成放大器，连接在MISFET的漏极区域之间的负载电阻，MISFET串联连接的电源以及通过MISFET的栅极彼此连接的直流阻断电容器。该放大器具有一个栅极电容，其一端由在衬底中形成良好并且连接到电源的高压侧而构成，而另一个电极由形成在阱上并连接到低电压的栅电极构成侧电源。电容器的寄生电容大大降低，以允许放大器的更宽范围的频率调整。

4. 发明授权

US4100502A Class B FET amplifier circuit 失效
标题翻译： B类FET放大电路
公开(公告)号：US4100502A
公开(公告)日：1978-07-11
申请号：US719238
申请日：1976-08-31
申请人： Osamu Yamashiro
发明人： Osamu Yamashiro
IPC分类号： G04F5/06 , H01L21/822 , H01L27/04 , H03B5/36 , H03F3/20 , H03F3/213 , H03F3/30 , H03F3/34 , H03F3/345 , H03F3/347 , H03K19/0948 , H03F3/16
CPC分类号： G04F5/06 , H03F3/3028 , H03K19/0948
摘要： A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.
摘要翻译：一种互补逆变器放大器电路，包括互连反相器，其包括连接到第一源电位的p沟道MIS FET，连接到第二源极电位的n沟道MIS FET，两个FET的栅极被施加公共线性输入，连接到互补FET的漏极的各个负载电阻器，从负载电阻器的互连点或FET的漏极导出的输出以及连接在每个互补FET的栅极和漏极之间的偏置电阻器，该输入通过相应的电容器提供给FET的栅极。 p沟道FET和n沟道FET被单独偏置，使得该电路可以用作低功耗的B类推挽放大器。

5. 发明授权

US4032864A Electronic circuit having a misfet as an amplifying element 失效
标题翻译：具有作为放大元件的MISFET的电子电路
公开(公告)号：US4032864A
公开(公告)日：1977-06-28
申请号：US658067
申请日：1976-02-13
申请人： Osamu Yamashiro , Yoshikazu Hatsukano
发明人： Osamu Yamashiro , Yoshikazu Hatsukano
IPC分类号： G04C3/00 , G04C10/00 , G04F5/06 , H03B5/36 , H03F1/30 , H03F3/187 , H03K3/354 , H03F3/16
CPC分类号： H03K3/3545 , G04C3/00 , G04F5/06 , H03B5/364 , H03F1/308 , H03F3/187
摘要： In an electronic circuit such as MIS oscillation or amplifier circuit in which a MISFET or MISFET's is used as an amplifying element and a bias resistor is provided between input and output sides, a divided voltage of a power voltage determined by capacitive elements provided at the input side is selected to be equal to a bias voltage determined by the bias resistor, thereby preventing influence due to the variation in power voltage.

6. 发明授权

US4029973A Voltage booster circuit using level shifter composed of two complementary MIS circuits 失效
标题翻译：使用由两个互补MIS电路组成的电平转换器的升压电路
公开(公告)号：US4029973A
公开(公告)日：1977-06-14
申请号：US674084
申请日：1976-04-06
申请人： Isamu Kobayashi , Osamu Yamashiro , Naoki Yashiki , Tadashi Funakubo
发明人： Isamu Kobayashi , Osamu Yamashiro , Naoki Yashiki , Tadashi Funakubo
IPC分类号： H03K5/02 , G04G19/04 , H02M3/07 , H02M3/155 , H03K1/14 , G04C3/00 , H03K3/353 , H03K17/60
CPC分类号： H02M3/07 , G04G19/04
摘要： This specification discloses an improvement for a voltage booster circuit. The improvement lies mainly in the use of MISFETs as switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.
摘要翻译：本说明书公开了对升压电路的改进。该改进主要在于在互补的MIS半导体集成电路中构成的电平转换电路中使用MISFET作为开关装置，因此可以防止由于传统的开关装置引起的电压损失。

7. 发明授权

US4553098A Battery checker 失效
标题翻译：电池检查器
公开(公告)号：US4553098A
公开(公告)日：1985-11-12
申请号：US484263
申请日：1983-04-12
申请人： Kanji Yoh , Osamu Yamashiro
发明人： Kanji Yoh , Osamu Yamashiro
IPC分类号： G05F3/24 , G11C5/14 , G11C11/411 , G11C11/417 , H01L27/088 , H01L29/49 , H03F3/45 , H03K3/0231 , H03K3/0233 , H03K3/3565 , H03K5/24 , H03K19/003 , H03K19/0185 , G01N27/46
CPC分类号： H03K19/00384 , G05F3/245 , G11C11/4113 , G11C11/417 , G11C5/143 , G11C5/147 , H01L27/088 , H01L29/4983 , H03F3/45179 , H03F3/45744 , H03F3/45748 , H03K19/018507 , H03K19/018514 , H03K3/0231 , H03K3/02337 , H03K3/3565 , H03K5/2481 , H03F2203/45394
摘要： A battery checker utilizes a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, but which have Fermi energy levels of values different from each other.
摘要翻译：电池检查器利用检测与半导体的能隙对应的电压或与其接近的值的电压的基准电压发生器装置或基于半导体的能级的电压，并将检测到的电压作为参考电压。通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导电类型的半导体和由相同半导体材料制成的本征半导体，但具有费米的两个半导体能量水平值彼此不同。

8. 发明授权

US4322639A Voltage detection circuit 失效
标题翻译：电压检测电路
公开(公告)号：US4322639A
公开(公告)日：1982-03-30
申请号：US886425
申请日：1978-03-14
申请人： Osamu Yamashiro
发明人： Osamu Yamashiro
IPC分类号： G01R19/165 , G04C10/04 , H03K5/24 , H03K5/153
CPC分类号： G01R19/16519 , G04C10/04 , H03K5/249
摘要： A voltage detection circuit adapted for use in an electronic timepiece in which a source voltage from a battery power source, etc. is voltage-divided and applied to an input of a logic circuit including complementary MIS FETs so as to compare the divided source voltage with a reference potential level and to detect whether the source voltage is above a predetermined value or not. In the logic circuit, the logic threshold is set in the neighborhood of the threshold voltage of one MIS FET to establish a reference potential level. Advantages are provided in integrating the circuit in a semiconductor integrated circuit such that parameters relevant to the manufacturing processes do not influence the reference potential level very much and the dispersion in the detected voltage due to the fluctuations in the manufacturing processes are minimized.
摘要翻译：一种适用于电子计时器的电压检测电路，其中来自电池电源等的源电压被分压并施加到包括互补MIS FET的逻辑电路的输入端，以便将分压的源极电压与参考电位电平并检测源极电压是否高于预定值。在逻辑电路中，将逻辑阈值设置在一个MIS FET的阈值电压附近，以建立参考电位电平。提供了将电路集成在半导体集成电路中的优点，使得与制造工艺相关的参数不会非常影响参考电位电平，并且由于制造过程中的波动而使检测到的电压的偏差最小化。

9. 发明授权

US4211985A Crystal oscillator using a class B complementary MIS amplifier 失效
标题翻译：晶体振荡器采用B类互补的MIS放大器
公开(公告)号：US4211985A
公开(公告)日：1980-07-08
申请号：US900321
申请日：1978-04-26
申请人： Osamu Yamashiro
发明人： Osamu Yamashiro
IPC分类号： G04F5/06 , H03B5/36 , H03F3/30 , H03K19/0948
CPC分类号： H03F3/3028 , G04F5/06 , H03B5/364 , H03K19/0948
摘要： In oscillators such as those used in electronic watches, low power consumption is quite desirable. To accomplish this, an oscillator is provided including a complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, and the gate of the two FETs being applied with a common linear input. Respective load resistors are connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs. Further, a bias resistor is connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.
摘要翻译：在诸如用于电子手表的振荡器中，低功耗是非常可取的。为了实现这一点，提供了一种振荡器，其包括互补反相放大器电路，其包括互连反相器，该互补反相器包括连接到第一源极电位的p沟道MIS FET，连接到第二源极电位的n沟道MIS FET，以及栅极两个FET被施加一个共同的线性输入。各个负载电阻连接到互补FET的漏极，输出源自负载电阻器的互连点或FET的漏极。此外，偏置电阻器连接在每个互补FET的栅极和漏极之间，输入通过相应的电容器提供给FET的栅极。 p沟道FET和n沟道FET被单独偏置，使得该电路可以用作低功耗的B类推挽放大器。

10. 发明授权

US4031456A Constant-current circuit 失效
标题翻译：恒流电路
公开(公告)号：US4031456A
公开(公告)日：1977-06-21
申请号：US608731
申请日：1975-08-28
申请人： Shunji Shimada , Yoshikazu Hatsukano , Osamu Yamashiro
发明人： Shunji Shimada , Yoshikazu Hatsukano , Osamu Yamashiro
IPC分类号： G05F3/24 , G05F3/08
CPC分类号： G05F3/247
摘要： A constant-current circuit has a depletion type FET and a series circuit consisting of an impedance element and an enhancement type FET connected in parallel between two terminals. The gate electrodes of the respective FET's are connected to a juncture between the impedance element and the enhancement type FET, and current which flows through the depletion type FET is set to be sufficiently larger than a current which flows through the series circuit. The voltage across the enhancement type FET is made substantially equal to a threshold voltage thereof, whereby the constant current characteristics of such constant-current circuits are checked from being dispersed.
摘要翻译：恒流电路具有耗尽型FET和由两个端子之间并联连接的阻抗元件和增强型FET组成的串联电路。各个FET的栅电极连接到阻抗元件和增强型FET之间的接合处，并且流过耗尽型FET的电流被设定为充分大于流过串联电路的电流。使增强型FET两端的电压基本上等于其阈值电压，从而分散这些恒流电路的恒定电流特性。

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