专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08339845B2 Flash memory device, programming method and memory system 有权
标题翻译：闪存设备，编程方法和存储系统
公开(公告)号：US08339845B2
公开(公告)日：2012-12-25
申请号：US12719189
申请日：2010-03-08
申请人： Oh Suk Kwon
发明人： Oh Suk Kwon
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line.
摘要翻译：提供了一种闪存设备中的编程方法。编程方法将第一遍电压施加到选择字线和非选择字线，向非选择字线施加本地电压，向选择字线施加第二通过电压，并将编程电压施加到选择字线。

2. 发明申请

US20100246259A1 FLASH MEMORY DEVICE, PROGRAMMING METHOD AND MEMORY SYSTEM 有权
标题翻译：闪存存储器件，编程方法和存储器系统
公开(公告)号：US20100246259A1
公开(公告)日：2010-09-30
申请号：US12719189
申请日：2010-03-08
申请人： Oh Suk KWON
发明人： Oh Suk KWON
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： Provided is a programming method in a flash memory device. The programming method applies a first pass voltage to a selection word line and a non-selection word line, applies a local voltage to the non-selection word line, applies a second pass voltage to the selection word line, and applies a programming voltage to the selection word line.
摘要翻译：提供了一种闪存设备中的编程方法。编程方法将第一遍电压施加到选择字线和非选择字线，向非选择字线施加本地电压，向选择字线施加第二通过电压，并将编程电压施加到选择字线。

3. 发明授权

US07738297B2 Method and apparatus for controlling two or more non-volatile memory devices 失效
标题翻译：用于控制两个或更多个非易失性存储器件的方法和装置
公开(公告)号：US07738297B2
公开(公告)日：2010-06-15
申请号：US12036416
申请日：2008-02-25
申请人： Oh Suk Kwon , Sung Soo Lee , Duck Kyeun Woo
发明人： Oh Suk Kwon , Sung Soo Lee , Duck Kyeun Woo
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G06F13/1647
摘要： A method and apparatus for controlling two or more non-volatile memory devices includes activating a read enable signal or a write enable signal, which is input to the first and second non-volatile memory devices, using a controller. A first chip enable signal is alternately activated for selecting the first non-volatile memory device and a second chip enable signal is activated for selecting the second non-volatile memory device using the controller. This is done while the read enable signal or the write enable signal is input to the first and second non-volatile memory devices being activated. Accordingly, even when the minimum cycle of the controller is longer than that of a memory device read/write time is reduced, thereby improving read/write performance.
摘要翻译：用于控制两个或多个非易失性存储器件的方法和装置包括使用控制器激活输入到第一和第二非易失性存储器件的读使能信号或写使能信号。交替激活第一芯片使能信号以选择第一非易失性存储器件，并激活第二芯片使能信号，以使用控制器选择第二非易失性存储器件。这是在将读取使能信号或写入使能信号输入到被激活的第一和第二非易失性存储器件时完成的。因此，即使当控制器的最小周期长于存储器件的最小周期时，读/写时间也减少，从而提高读/写性能。

4. 发明授权

US07717842B2 Apparatus and method for generating pulsating noise in audio device 有权
标题翻译：用于在音频设备中产生脉动噪声的装置和方法
公开(公告)号：US07717842B2
公开(公告)日：2010-05-18
申请号：US11037258
申请日：2005-01-19
申请人： Oh Suk Kwon , Jong Woo Kim
发明人： Oh Suk Kwon , Jong Woo Kim
IPC分类号： A61M21/00
CPC分类号： A61M21/00 , A61M2021/0027
摘要： An apparatus and method for generating pulsating noise in an audio device are provided. The apparatus and method mix audio signals processed by an audio play operation with pulsating noise generated by a pulsating noise generator if a brain wave induction mode is set in an audio device and output a result of the mixing operation through wired or wireless speaker. Therefore, a user can efficiently experience brain wave induction action based on the pulsating noise while he/she hears audio from the speaker.
摘要翻译：提供了一种在音频设备中产生脉动噪声的装置和方法。如果在音频装置中设置脑波感应模式并且通过有线或无线扬声器输出混合操作的结果，则该装置和方法将由音频播放操作处理的音频信号与由脉动噪声发生器产生的脉动噪声混合。因此，当用户听到来自扬声器的音频时，用户可以基于脉动噪声有效地体验脑波感应动作。

5. 发明授权

US07596026B2 Program method of non-volatile memory device 有权
标题翻译：非易失性存储器件的程序方法
公开(公告)号：US07596026B2
公开(公告)日：2009-09-29
申请号：US11679072
申请日：2007-02-26
申请人： Oh-Suk Kwon , June Lee
发明人： Oh-Suk Kwon , June Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： A program method of a non-volatile memory device comprises setting a string select line to a predetermined voltage, setting a selected word line to a program voltage and unselected word lines to a pass voltage respectively. The program voltage is varied according to an arrangement of the selected word line. Problems arising from capacitive coupling between adjacent signal lines are alleviated.
摘要翻译：非易失性存储器件的编程方法包括将串选择线设置为预定电压，将所选择的字线设置为编程电压，将未选字线设置为通过电压。编程电压根据所选字线的布置而变化。相邻信号线之间电容耦合产生的问题得到缓解。

6. 发明申请

US20090067250A1 MEMORY DEVICES WITH PAGE BUFFER HAVING DUAL REGISTERS AND METHOD OF USING THE SAME 有权
标题翻译：具有双寄存器的页面缓冲器的存储器件及其使用方法
公开(公告)号：US20090067250A1
公开(公告)日：2009-03-12
申请号：US12271557
申请日：2008-11-14
申请人： June LEE , Oh-Suk KWON , Heung-Soo IM
发明人： June LEE , Oh-Suk KWON , Heung-Soo IM
IPC分类号： G11C16/06 , G11C8/00
CPC分类号： G11C7/1093 , G11C7/1006 , G11C7/1021 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/26 , G11C16/3454 , G11C16/3459 , G11C2207/002 , G11C2216/14
摘要： A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.
摘要翻译：因此，描述了包括具有第一和第二数据寄存器或锁存器的可操作耦合的第一和第二读出放大器的非易失性存储器件和编程方法和装置，用于存储第二放大器的数据的存储电路，用于检查的通过/失败检查电路第二数据寄存器的内容是存储器件的单元是否已经被充分地编程，以及恢复电路，用于复位第二数据寄存器以重新编程器件直到充分编程。

7. 发明申请

US20080191786A1 HIGH VOLTAGE GENERATION CIRCUIT AND METHOD FOR GENERATING HIGH VOLTAGE 审中-公开
标题翻译：高电压发生电路及高压发生方法
公开(公告)号：US20080191786A1
公开(公告)日：2008-08-14
申请号：US11962479
申请日：2007-12-21
申请人： Oh Suk Kwon , Ki Hwan Choi
发明人： Oh Suk Kwon , Ki Hwan Choi
IPC分类号： G05F3/02
CPC分类号： H02M3/073 , H02M2003/077
摘要： A high voltage generation circuit includes a delay circuit configured to generate multiple delay clock signals based on a clock signal. The delay clock signals include corresponding different predetermined delay times. The high voltage generation circuit further includes multiple pumps corresponding to the delay clock signals. The pumps are configured to perform a charge pumping operation in response to the corresponding delay clock signals to generate a high voltage.
摘要翻译：高电压产生电路包括：延迟电路，被配置为基于时钟信号产生多个延迟时钟信号。延迟时钟信号包括相应的不同的预定延迟时间。高电压发生电路还包括对应于延迟时钟信号的多个泵。泵被配置为响应于相应的延迟时钟信号执行电荷泵送操作以产生高电压。

8. 发明授权

US07379351B2 Non-volatile semiconductor memory and programming method 有权
标题翻译：非易失性半导体存储器和编程方法
公开(公告)号：US07379351B2
公开(公告)日：2008-05-27
申请号：US11471541
申请日：2006-06-21
申请人： Oh Suk Kwon , Dae Seok Byeon
发明人： Oh Suk Kwon , Dae Seok Byeon
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C16/0483
摘要： In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells. The method includes a primary programming process which includes providing a first program voltage to a selected memory cell to program the selected memory cell, a verify read process which includes reading the selected memory cell to verify a programmed status of the selected memory cell resulting from the primary programming process, and a secondary programming process which includes providing a second program voltage to the selected memory cell so as to reprogram the selected memory cell after the verify read process. During the verify read process, the transmission transistors are continuously gated by a boosted voltage generated during the primary programming process. The boosted voltage has a voltage level which is sufficient to provide the first and second program voltages to the memory cell.
摘要翻译：在一个方面，提供一种用于非易失性半导体存储器件的编程方法，该非易失性半导体存储器件包括多个电可编程和可擦除存储器单元，以及用于向存储器单元提供预定电压的传输晶体管。该方法包括主编程过程，其包括向所选择的存储器单元提供第一编程电压以对所选择的存储器单元进行编程;验证读取处理，其包括读取所选择的存储器单元，以验证所选存储器单元的编程状态，主编程处理和辅助编程处理，其包括向所选择的存储器单元提供第二编程电压，以便在验证读取处理之后重新编程所选择的存储器单元。在验证读取过程期间，传输晶体管由主要编程过程中产生的升压电压连续选通。升压电压具有足以向存储单元提供第一和第二编程电压的电压电平。

9. 发明授权

US06967868B2 Semiconductor memory device having flexible column redundancy scheme 有权
标题翻译：具有灵活的列冗余方案的半导体存储器件
公开(公告)号：US06967868B2
公开(公告)日：2005-11-22
申请号：US10845314
申请日：2004-05-14
申请人： In-Young Kim , June Lee , Oh-Suk Kwon
发明人： In-Young Kim , June Lee , Oh-Suk Kwon
IPC分类号： G11C16/02 , G11C5/02 , G11C11/34 , G11C16/06 , G11C29/00
CPC分类号： G11C29/846 , G11C29/781 , G11C2029/1802
摘要： A flash memory device may include: a plurality of main bit lines; a plurality of redundant bit lines; a plurality of first page buffers respectively organized as a plurality of first page buffer groups which are connected to main bit lines; a plurality of second page buffers respectively organized as a plurality of second page buffer groups which are connected to the redundant bit lines; each of the first and second page buffers including an output P/F terminal to provide pass/fail data; a plurality of fuses corresponding to the pluralities of the first and second page buffer groups, respectively, each of the fuses having one end commonly connected to the P/F terminals in a corresponding page buffer group and the other end connected to a signal line; and a pass/fail check circuit to determine an overall pass/fail signal based upon a signal on the signal line.
摘要翻译：闪存器件可以包括：多个主位线; 多个冗余位线; 分别组织成连接到主位线的多个第一页缓冲器组的多个第一页缓冲器; 多个第二页缓冲器分别被组织为连接到冗余位线的多个第二页缓冲器组; 第一和第二页缓冲器中的每一个包括用于提供通过/不合格数据的输出P / F端子; 分别对应于多个第一和第二寻呼缓冲器组的多个保险丝，每个保险丝的一端在对应的页缓冲器组中共同连接到P / F端子，另一端连接到信号线; 以及通过/失败检查电路，以基于信号线上的信号确定总体通过/失败信号。

10. 发明申请

US20050117399A1 Flash memory devices and methods for programming the same 有权
标题翻译：闪存设备和编程方法相同
公开(公告)号：US20050117399A1
公开(公告)日：2005-06-02
申请号：US10965446
申请日：2004-10-14
申请人： Oh-Suk Kwon , June Lee
发明人： Oh-Suk Kwon , June Lee
IPC分类号： G11C16/02 , G11C8/08 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/10 , G11C8/08 , G11C16/0483 , G11C2216/14
摘要： A flash memory device having a memory cell string is programmed. The flash memory device includes a plurality of memory cells. During a programming cycle, application of a program voltage to a channel region of the plurality of memory cells is delaying until after a gate of each of the memory cells of the plurality of memory cells that is to be programmed has reached a programming voltage Vpgm.
摘要翻译：具有存储单元串的闪速存储器件被编程。闪存装置包括多个存储单元。在编程周期期间，将程序电压施加到多个存储单元的通道区域是延迟的，直到待编程的多个存储器单元的每个存储单元的栅极已经达到编程电压Vpgm为止。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式