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1. 发明授权

US5719066A Method of manufacturing a semiconductor integrated circuit apparatus having a mis-type condenser 失效
标题翻译：制造具有错误型冷凝器的半导体集成电路装置的方法
公开(公告)号：US5719066A
公开(公告)日：1998-02-17
申请号：US625284
申请日：1996-04-01
申请人： Yoshiaki Sano , Toshimasa Sadakata , Yasunari Tagami , Yasuo Oishibashi
发明人： Yoshiaki Sano , Toshimasa Sadakata , Yasunari Tagami , Yasuo Oishibashi
IPC分类号： H01L27/04 , H01L21/334 , H01L27/06 , H01L21/265
CPC分类号： H01L29/66181 , H01L27/0664
摘要： A lower layer diffusion layer of a metal-insulator-semiconductor-type (MIS-type) condenser is formed by implanting and diffusing phosphorus into an upper portion of an epitaxial layer formed on a semiconductor substrate. Thereafter, a silicon nitride film functioning as a dielectric film of the MIS type condenser is formed on the lower layer diffusion layer, and a poly-silicon film functioning as a protective film for the silicon nitride film is formed on the silicon nitride film in succession to the formation of the silicon nitride film without performing any etching operation. The formation of the silicon nitride film and the poly-silicon film is performed according to a vacuum chemical vapor deposition in the same chamber to prevent the silicon nitride film from being exposed to oxygen. Thereafter, the silicon nitride film and the poly-silicon film are baked to form an oxidized film surrounding the silicon nitride film and the poly-silicon film. Thereafter, a metal is deposited on the poly-silicon film to form an upper electrode of the MIS type condenser. Therefore, the deterioration of dielectric characteristics of the MIS type condenser can be prevented.
摘要翻译：通过将磷注入并扩散到形成在半导体衬底上的外延层的上部来形成金属 - 绝缘体半导体型（MIS型）电容器的下层扩散层。此后，在下层扩散层上形成用作MIS型电容器的电介质膜的氮化硅膜，并且在氮化硅膜上连续形成用作氮化硅膜的保护膜的多晶硅膜以形成氮化硅膜而不执行任何蚀刻操作。根据在相同的室中的真空化学气相沉积来进行氮化硅膜和多晶硅膜的形成，以防止氮化硅膜暴露于氧气。然后，对氮化硅膜和多晶硅膜进行焙烧，形成围绕氮化硅膜和多晶硅膜的氧化膜。此后，在多晶硅膜上沉积金属以形成MIS型冷凝器的上电极。因此，可以防止MIS型冷凝器的介电特性的劣化。

2. 发明授权

US4898839A Semiconductor integrated circuit and manufacturing method therefor 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US4898839A
公开(公告)日：1990-02-06
申请号：US271746
申请日：1988-11-15
申请人： Chikao Fujinuma , Nobuyuki Sekikawa , Teruo Tabata , Tadayoshi Takada , Yoshiaki Sano , Toshimasa Sadakata
发明人： Chikao Fujinuma , Nobuyuki Sekikawa , Teruo Tabata , Tadayoshi Takada , Yoshiaki Sano , Toshimasa Sadakata
IPC分类号： H01L21/761 , H01L21/8248 , H01L27/06
CPC分类号： H01L21/761 , H01L21/8248 , H01L27/0658 , Y10S148/014
摘要： A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.
摘要翻译：一种制造半导体集成电路的方法包括以下步骤：形成覆盖半导体衬底和掩埋层的外延层; 形成将外延层分成多个岛的隔离区; 在其中一个岛中形成MIS型电容器的下电极区域; 在另一岛中与下电极同时或独立地形成垂直双极晶体管的基极区; 在所述下电极区域的一部分上沉积所述MIS型电容器的薄介电层; 然后选择性地将杂质扩散到基极区的表面层中，以形成垂直双极晶体管的发射极区; 以及在所述薄介电层上形成所述MIS型电容器的上电极。

3. 发明授权

US5141881A Method for manufacturing a semiconductor integrated circuit 失效
标题翻译：制造半导体集成电路的方法
公开(公告)号：US5141881A
公开(公告)日：1992-08-25
申请号：US510469
申请日：1990-04-18
申请人： Kazuo Takeda , Toshimasa Sadakata , Teruo Tabata , Nobuyuki Sekikawa , Tadayoshi Takada , Yasuhiro Tamada , Yoshiaki Sano
发明人： Kazuo Takeda , Toshimasa Sadakata , Teruo Tabata , Nobuyuki Sekikawa , Tadayoshi Takada , Yasuhiro Tamada , Yoshiaki Sano
IPC分类号： H01L21/761 , H01L21/8222
CPC分类号： H01L21/761 , H01L21/8222 , Y10S148/009 , Y10S148/01
摘要： A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

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