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1. 发明申请

US20140024220A1 METHOD OF FABRICATING AN ULTRA LOW-K DIELECTRIC SELF-ALIGNED VIA 有权
标题翻译：制造超低K电介质自对准方法
公开(公告)号：US20140024220A1
公开(公告)日：2014-01-23
申请号：US13724698
申请日：2012-12-21
申请人： Chih-Yang Chang , Sean S. Kang , Chia-Ling Kao , Nikolaos Bekiaris
发明人： Chih-Yang Chang , Sean S. Kang , Chia-Ling Kao , Nikolaos Bekiaris
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/3105 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.
摘要翻译：描述了制造超低k电介质自对准通孔的方法。在一个示例中，在低k电介质膜中形成自对准通孔（SAV）的方法包括在形成在衬底上方的低k电介质膜上形成的金属氮化物硬掩模层中形成沟槽图案。在形成在金属氮化物硬掩模层之上的掩模层中形成通孔图案。通孔图案至少部分地被蚀刻到低k电介质膜中，蚀刻包括使用基于CF4，H2和稀释惰性气体组成的化学物质进行等离子体蚀刻。

2. 发明授权

US07226853B2 Method of forming a dual damascene structure utilizing a three layer hard mask structure 失效
标题翻译：使用三层硬掩模结构形成双镶嵌结构的方法
公开(公告)号：US07226853B2
公开(公告)日：2007-06-05
申请号：US10197936
申请日：2002-07-16
申请人： Nikolaos Bekiaris , Timothy Weidman , Michael D. Armacost , Mehul B. Naik
发明人： Nikolaos Bekiaris , Timothy Weidman , Michael D. Armacost , Mehul B. Naik
IPC分类号： H01L21/4763
CPC分类号： H01L21/022 , H01L21/02115 , H01L21/02126 , H01L21/02203 , H01L21/0332 , H01L21/31144 , H01L21/312 , H01L21/3146 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835
摘要： A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer; depositing a second hard mask layer on the first hard mask layer; depositing a third hard mask layer on the second hard mask layer and completing formation of the dual damascene structure by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one particular embodiment the second hard mask layer is an amorphous carbon layer and the third hard mask layer is a silicon-containing material.
摘要翻译：在其上已经形成有电介质层的基板上形成双镶嵌结构的方法。在一个实施例中，该方法包括在介电层上沉积第一硬掩模层; 在第一硬掩模层上沉积第二硬掩模层; 在第二硬掩模层上沉积第三硬掩模层，并通过蚀刻电介质层中的金属布线图案和通孔图案并用导电材料填充蚀刻的金属布线图案和通孔图案，完成双镶嵌结构的形成。在一个特定实施例中，第二硬掩模层是无定形碳层，第三硬掩模层是含硅材料。

3. 发明授权

US06991739B2 Method of photoresist removal in the presence of a dielectric layer having a low k-value 有权
公开(公告)号：US06991739B2
公开(公告)日：2006-01-31
申请号：US09978121
申请日：2001-10-15
申请人： Mark N. Kawaguchi , Huong T. Nguyen , Nikolaos Bekiaris , James S. Papanu
发明人： Mark N. Kawaguchi , Huong T. Nguyen , Nikolaos Bekiaris , James S. Papanu
IPC分类号： H01L21/00
CPC分类号： H01L21/02063 , G03F7/427 , H01L21/31138
摘要： A method of photoresist removal is described. A substrate is located in a processing chamber. A mixture of gases is excited, the mixture comprising a majority component of a reducing process gas and a minority component of between 0.1% and 10% by volume of an oxidizing process gas. Reactive gas species are thereby generated. A photoresist layer with an exposed dielectric layer on the substrate in the chamber is then exposed to the reactive gas mixture to selectively remove the photoresist layer from the dielectric layer.

4. 发明授权

US06806203B2 Method of forming a dual damascene structure using an amorphous silicon hard mask 失效
标题翻译：使用非晶硅硬掩模形成双镶嵌结构的方法
公开(公告)号：US06806203B2
公开(公告)日：2004-10-19
申请号：US10101540
申请日：2002-03-18
申请人： Timothy Weidman , Nikolaos Bekiaris , Josephine Chang , Phong H. Nguyen
发明人： Timothy Weidman , Nikolaos Bekiaris , Josephine Chang , Phong H. Nguyen
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L21/76829
摘要： A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.
摘要翻译：在其上已经形成有电介质层的基板上形成双镶嵌结构的方法。在一个实施例中，该方法包括在电介质层上沉积第一硬掩模层并在第一硬掩模层上沉积第二硬掩模层，其中第二硬掩模层是非晶硅层。然后，通过在电介质层中蚀刻金属布线图案和通孔图案并用导电材料填充蚀刻的金属布线图案和通孔图案来完成双镶嵌结构的形成。

5. 发明申请

US20080032426A1 METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS 有权
标题翻译：用于控制轨迹切削工具中关键尺寸的方法和系统
公开(公告)号：US20080032426A1
公开(公告)日：2008-02-07
申请号：US11834518
申请日：2007-08-06
申请人： Timothy Michaelson , Nikolaos Bekiaris
发明人： Timothy Michaelson , Nikolaos Bekiaris
IPC分类号： H01L21/66 , B05C11/00
CPC分类号： H01L22/20 , H01L22/12
摘要： A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation.
摘要翻译：控制轨道光刻工具上的晶片临界尺寸（CD）均匀性的方法包括获得晶片的CD图。 CD映射包括与多区加热器几何图相关的多个CD数据点。多区加热器包括多个加热区。该方法还包括基于CD数据点中的一个或多个来确定多个加热器区域中的第一加热器区域的CD值，并计算所确定的第一加热器区域的CD值与用于第一加热器区域的目标CD值之间的差值第一加热区。该方法还包括：部分地基于计算出的差异和沉积在晶片上的光致抗蚀剂的温度敏感度来确定第一加热器区域的温度变化，并且部分地基于温度改变第一加热器区域的温度变异。

6. 发明授权

US07265062B2 Ionic additives for extreme low dielectric constant chemical formulations 失效
标题翻译：用于极低介电常数化学配方的离子添加剂
公开(公告)号：US07265062B2
公开(公告)日：2007-09-04
申请号：US10636517
申请日：2003-08-07
申请人： Robert P. Mandal , Alexandros T. Demos , Timothy Weidman , Michael P. Nault , Nikolaos Bekiaris , Scott Jeffrey Weigel , Lee A. Senecal , James E. Mac Dougall , Hareesh Thridandam
发明人： Robert P. Mandal , Alexandros T. Demos , Timothy Weidman , Michael P. Nault , Nikolaos Bekiaris , Scott Jeffrey Weigel , Lee A. Senecal , James E. Mac Dougall , Hareesh Thridandam
IPC分类号： H01L21/31
CPC分类号： H01L21/02126 , C01B33/16 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/31695
摘要： A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.
摘要翻译：一种使用溶胶 - 凝胶方法沉积多孔氧化硅基膜的方法，该方法使用前体溶液制剂，其包含纯化的非离子表面活性剂和其它组分中的添加剂，其中添加剂是形成离子的离子添加剂或胺添加剂铵型盐在酸性前体溶液中。使用这种前体溶液制剂可以形成介电常数小于2.5，适当的机械性能和最低水平的碱金属杂质的薄膜。在一个实施方案中，这通过纯化表面活性剂并将离子或胺添加剂例如四烷基铵盐和胺添加到原料前体溶液中来实现。

7. 发明授权

US07244683B2 Integration of ALD/CVD barriers with porous low k materials 有权
标题翻译： ALD / CVD屏障与多孔低k材料的集成
公开(公告)号：US07244683B2
公开(公告)日：2007-07-17
申请号：US10741422
申请日：2003-12-19
申请人： Hua Chung , Nikolaos Bekiaris , Christophe Marcadal , Ling Chen
发明人： Hua Chung , Nikolaos Bekiaris , Christophe Marcadal , Ling Chen
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/76843 , C23C16/34 , H01L21/02063 , H01L21/28556 , H01L21/28562 , H01L21/31116 , H01L21/76802 , H01L21/76814 , H01L21/76838 , H01L21/76873 , H01L21/76876
摘要： A method for processing substrates is provided. The method includes depositing and etching a low k dielectric layer on a substrate, pre-cleaning the substrate with a plasma, and depositing a barrier layer on the substrate. Pre-cleaning the substrate minimizes the diffusion of the barrier layer into the low k dielectric layer and/or enhances the deposition of the barrier layer.
摘要翻译：提供了一种处理衬底的方法。该方法包括沉积和蚀刻基底上的低k电介质层，用等离子体预清洁衬底，以及在衬底上沉积阻挡层。预清洁衬底使阻挡层向低k电介质层的扩散最小化和/或增强阻挡层的沉积。

8. 发明授权

US06576568B2 Ionic additives for extreme low dielectric constant chemical formulations 失效
公开(公告)号：US06576568B2
公开(公告)日：2003-06-10
申请号：US09823932
申请日：2001-03-29
申请人： Robert P Mandal , Alexandros T Demos , Timothy Weidman , Michael P Nault , Nikolaos Bekiaris , Scott J Weigel , Lee A. Senecal , James E. MacDougall , Hareesh Thridandam
发明人： Robert P Mandal , Alexandros T Demos , Timothy Weidman , Michael P Nault , Nikolaos Bekiaris , Scott J Weigel , Lee A. Senecal , James E. MacDougall , Hareesh Thridandam
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C01B33/16 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/31695 , Y10S438/96 , Y10T428/249953 , Y10T428/249969
摘要： A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution. In some embodiments, the ionic additive is a compound chosen from a group of cationic additives of the general composition [NR(CH3)3]+A−, where R is a hydrophobic ligand of chain length 1 to 24, including tetramethylammonium and cetyltrimethylammonium, and A− is an anion, which may be chosen from the group consisting essentially of formate, nitrate, oxalate, acetate, phosphate, carbonate, and hydroxide and combinations thereof. Tetramethylammonium salts, or more generally tetraalkylammonium salts, or tetraorganoammonium salts or organoamines in acidic media are added to surfactant templated porous oxide precursor formulations to increase the ionic content, replacing alkali ion impurities (sodium and potassium) removed during surfactant purification, but which are found to exhibit beneficial effects in promoting the formation of the resulting dielectric.

9. 发明申请

US20090275149A1 METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS 审中-公开
标题翻译：用于控制轨迹切削工具中关键尺寸的方法和系统
公开(公告)号：US20090275149A1
公开(公告)日：2009-11-05
申请号：US12261732
申请日：2008-10-30
申请人： Timothy Michaelson , Nikolaos Bekiaris
发明人： Timothy Michaelson , Nikolaos Bekiaris
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/12
摘要： A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation.
摘要翻译：控制轨道光刻工具上的晶片临界尺寸（CD）均匀性的方法包括获得晶片的CD图。 CD映射包括与多区加热器几何图相关的多个CD数据点。多区加热器包括多个加热区。该方法还包括基于CD数据点中的一个或多个来确定多个加热器区域中的第一加热器区域的CD值，并计算所确定的第一加热器区域的CD值与用于第一加热器区域的目标CD值之间的差值第一加热区。该方法还包括：部分地基于计算出的差异和沉积在晶片上的光致抗蚀剂的温度敏感度来确定第一加热器区域的温度变化，并且部分地基于温度改变第一加热器区域的温度变异。

10. 发明申请

US20090253078A1 DOUBLE EXPOSURE LITHOGRAPHY USING LOW TEMPERATURE OXIDE AND UV CURE PROCESS 审中-公开
标题翻译：使用低温氧化物和紫外线固化过程进行双重曝光
公开(公告)号：US20090253078A1
公开(公告)日：2009-10-08
申请号：US12415690
申请日：2009-03-31
申请人： Nikolaos Bekiaris , Junyan Dai , Hiram Cervera , Hali Janine Lana Forstner
发明人： Nikolaos Bekiaris , Junyan Dai , Hiram Cervera , Hali Janine Lana Forstner
IPC分类号： G03F7/20 , G03B27/62
CPC分类号： G03F7/0035 , G03B27/62 , G03F7/405 , G03F7/70466 , H01L21/0274 , H01L21/67225
摘要： A method of processing a substrate includes forming a first layer having a photosensitive response to incident radiation on the substrate, forming a first pattern in the first layer, and exposing the first pattern to ultra-violet radiation. The exposure of the first pattern to ultra-violet radiation increases the resistance of the first pattern to a developer. The method also includes forming a conformal protective layer over the first pattern and at least a portion of the substrate. The method further includes forming a second layer having a photosensitive response to incident radiation over the conformal protective layer and forming a second pattern in the second layer.
摘要翻译：一种处理衬底的方法包括形成对衬底上的入射辐射具有光敏响应的第一层，在第一层中形成第一图案，并将第一图案暴露于紫外辐射。将第一图案暴露于紫外线辐射会增加第一图案对显影剂的电阻。该方法还包括在第一图案和基底的至少一部分上形成共形保护层。该方法还包括形成具有对保形层上的入射辐射的感光响应的第二层，并在第二层中形成第二图案。

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