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1. 发明申请

US20140024220A1 METHOD OF FABRICATING AN ULTRA LOW-K DIELECTRIC SELF-ALIGNED VIA 有权
标题翻译：制造超低K电介质自对准方法
公开(公告)号：US20140024220A1
公开(公告)日：2014-01-23
申请号：US13724698
申请日：2012-12-21
申请人： Chih-Yang Chang , Sean S. Kang , Chia-Ling Kao , Nikolaos Bekiaris
发明人： Chih-Yang Chang , Sean S. Kang , Chia-Ling Kao , Nikolaos Bekiaris
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/3105 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814
摘要： Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.
摘要翻译：描述了制造超低k电介质自对准通孔的方法。在一个示例中，在低k电介质膜中形成自对准通孔（SAV）的方法包括在形成在衬底上方的低k电介质膜上形成的金属氮化物硬掩模层中形成沟槽图案。在形成在金属氮化物硬掩模层之上的掩模层中形成通孔图案。通孔图案至少部分地被蚀刻到低k电介质膜中，蚀刻包括使用基于CF4，H2和稀释惰性气体组成的化学物质进行等离子体蚀刻。

2. 发明授权

US08987139B2 Method of patterning a low-k dielectric film 有权
标题翻译：图案化低k电介质膜的方法
公开(公告)号：US08987139B2
公开(公告)日：2015-03-24
申请号：US14159832
申请日：2014-01-21
申请人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311 , H01L21/321 , H01L21/3213
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/321 , H01L21/32136 , H01L21/76802
摘要： Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实施例中，在一个实施例中，图案化低k电介质膜的方法涉及在低k电介质层上形成和图案化金属氮化物掩模层。低k电介质层设置在衬底之上。该方法还涉及通过用基于O 2 / N 2 / SixFy的等离子体处理钝化金属氮化物掩模层。该方法还涉及蚀刻低k电介质层的一部分。

3. 发明授权

US09006106B2 Method of removing a metal hardmask 有权
标题翻译：去除金属硬掩模的方法
公开(公告)号：US09006106B2
公开(公告)日：2015-04-14
申请号：US13889550
申请日：2013-05-08
申请人： Chia-Ling Kao , Kwang-soo Kim , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Kwang-soo Kim , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/32136 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L2221/1063
摘要： Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.
摘要翻译：描述了在超低k电介质膜存在下去除金属硬掩模的方法。在一个示例中，图案化低k电介质膜的方法包括在形成在衬底上方的低k电介质膜上形成的金属氮化物硬掩模层中形成图案。该方法还包括使用金属氮化物硬掩模层作为掩模的蚀刻，该图案至少部分地进入低k电介质膜，该蚀刻涉及使用基于SiFx的等离子体蚀刻。蚀刻还包括至少在蚀刻期间形成的低k电介质膜的侧壁上形成SiO x钝化层。该方法还包括通过干蚀刻工艺去除金属氮化物硬掩模层，其中SiO x钝化层在去除期间保护低k绝缘膜。

4. 发明申请

US20140213060A1 METHOD OF PATTERNING A LOW-K DIELECTRIC FILM 有权
标题翻译：绘制低K电介质膜的方法
公开(公告)号：US20140213060A1
公开(公告)日：2014-07-31
申请号：US14159832
申请日：2014-01-21
申请人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/321 , H01L21/32136 , H01L21/76802
摘要： Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实施例中，在一个实施例中，图案化低k电介质膜的方法涉及在低k电介质层上形成和图案化金属氮化物掩模层。低k电介质层设置在衬底之上。该方法还涉及通过用基于O 2 / N 2 / SixFy的等离子体处理钝化金属氮化物掩模层。该方法还涉及蚀刻低k电介质层的一部分。

5. 发明申请

US20140273496A1 METHOD OF REMOVING A METAL HARDMASK 有权
标题翻译：移除金属硬质合金的方法
公开(公告)号：US20140273496A1
公开(公告)日：2014-09-18
申请号：US13889550
申请日：2013-05-08
申请人： Chia-Ling Kao , Kwang-soo Kim , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Kwang-soo Kim , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/32136 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L2221/1063
摘要： Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.
摘要翻译：描述了在超低k电介质膜存在下去除金属硬掩模的方法。在一个示例中，图案化低k电介质膜的方法包括在形成在衬底上方的低k电介质膜上形成的金属氮化物硬掩模层中形成图案。该方法还包括使用金属氮化物硬掩模层作为掩模的蚀刻，该图案至少部分地进入低k电介质膜，该蚀刻涉及使用基于SiFx的等离子体蚀刻。蚀刻还包括至少在蚀刻期间形成的低k电介质膜的侧壁上形成SiO x钝化层。该方法还包括通过干蚀刻工艺去除金属氮化物硬掩模层，其中SiO x钝化层在去除期间保护低k绝缘膜。

6. 发明申请

US20080044995A1 Trilayer resist organic layer etch 有权
标题翻译：三层抗蚀剂有机层蚀刻
公开(公告)号：US20080044995A1
公开(公告)日：2008-02-21
申请号：US11507862
申请日：2006-08-21
申请人： Sean S. Kang , Sang Jun Cho , Tom Choi , Taejoon Han
发明人： Sean S. Kang , Sang Jun Cho , Tom Choi , Taejoon Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76808
摘要： A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.
摘要翻译：提供了一种在多孔低k电介质层中形成双镶嵌特征的方法。在多孔低k电介质层中形成通孔。在多孔低k电介质层上形成有机平坦化层，其中有机层填充通孔。在有机平坦化层上形成光致抗蚀剂掩模。特征被蚀刻到有机平坦化层中，包括提供含有CO 2的蚀刻气体，并从含有CO 2 2的蚀刻气体形成等离子体，其蚀刻有机平坦化层。使用有机平坦化层作为掩模将沟槽蚀刻到多孔低k电介质层中。剥离有机平坦化层。

7. 发明授权

US07192531B1 In-situ plug fill 有权
标题翻译：现场插头填充
公开(公告)号：US07192531B1
公开(公告)日：2007-03-20
申请号：US10603412
申请日：2003-06-24
申请人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , Reza Sadjadi
发明人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , Reza Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31138
摘要： A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.
摘要翻译：提供了一种用于在衬底上的阻挡层上的介电层中形成镶嵌特征的方法。在等离子体处理室中通过等离子体蚀刻工艺将多个通孔在电介质层中蚀刻到阻挡层。形成具有沟槽图案的图案化的光致抗蚀剂层。在单个等离子体处理室内，提供了通过插塞沉积的组合以在阻挡层上的通孔中形成插塞和沟槽蚀刻。

8. 发明授权

US06969685B1 Etching a dielectric layer in an integrated circuit structure having a metal hard mask layer 有权
标题翻译：在具有金属硬掩模层的集成电路结构中蚀刻介电层
公开(公告)号：US06969685B1
公开(公告)日：2005-11-29
申请号：US10246926
申请日：2002-09-18
申请人： SiYi Li , S. M. Reza Sadjadi , Sean S. Kang
发明人： SiYi Li , S. M. Reza Sadjadi , Sean S. Kang
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136
摘要： The invention relates to the etching of a dielectric layer in an integrated circuit (IC) structure having a patterned metal hard mask layer. The method comprises feeding a gas mixture that includes a carbon monoxide (CO) and at least one fluorocarbon gas mixture into a reactor. The gas mixture has no oxygen (O2) gas. The gas mixture is then converted into a plasma. The plasma selectively etches the dielectric layer. Typically, the dielectric layer comprises silicon.
摘要翻译：本发明涉及具有图案化金属硬掩模层的集成电路（IC）结构中的介电层的蚀刻。该方法包括将包含一氧化碳（CO）和至少一种碳氟化合物气体混合物的气体混合物进料到反应器中。气体混合物没有氧（O 2/2）气体。然后将气体混合物转化成等离子体。等离子体选择性地蚀刻介电层。通常，电介质层包括硅。

9. 发明授权

US08124516B2 Trilayer resist organic layer etch 有权
标题翻译：三层抗蚀剂有机层蚀刻
公开(公告)号：US08124516B2
公开(公告)日：2012-02-28
申请号：US11507862
申请日：2006-08-21
申请人： Sean S. Kang , Sang Jun Cho , Tom Choi , Taejoon Han
发明人： Sean S. Kang , Sang Jun Cho , Tom Choi , Taejoon Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76808
摘要： A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.
摘要翻译：提供了一种在多孔低k电介质层中形成双镶嵌特征的方法。在多孔低k电介质层中形成通孔。在多孔低k电介质层上形成有机平坦化层，其中有机层填充通孔。在有机平坦化层上形成光致抗蚀剂掩模。将特征蚀刻到有机平坦化层中，包括提供含CO 2的蚀刻气体并从含有CO 2的蚀刻气体形成等离子体，其蚀刻有机平坦化层。使用有机平坦化层作为掩模将沟槽蚀刻到多孔低k电介质层中。剥离有机平坦化层。

10. 发明授权

US07789991B1 Lag control 有权
标题翻译：滞后控制
公开(公告)号：US07789991B1
公开(公告)日：2010-09-07
申请号：US11810929
申请日：2007-06-07
申请人： Binet A. Worsham , Sean S. Kang , David Wei , Vinay Pohray , Bi Ming Yen
发明人： Binet A. Worsham , Sean S. Kang , David Wei , Vinay Pohray , Bi Ming Yen
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01L21/31116 , H01L21/31138
摘要： A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.
摘要翻译：一种用于在衬底上蚀刻基于氧化硅的电介质层中的特征的方法，包括执行蚀刻循环。执行基于氧化硅的电介质层中部分蚀刻部分蚀刻特征的延迟蚀刻，包括提供滞后的蚀刻剂气体，从滞后的蚀刻剂气体形成等离子体，并用滞后的蚀刻剂气体蚀刻蚀刻层，使得较小的特征被蚀刻更慢比更广泛的功能。执行反向延迟蚀刻进一步蚀刻基于氧化硅的电介质层中的特征，其包括提供与滞后蚀刻剂气体不同的反向滞后蚀刻剂气体，并且比滞后蚀刻剂气体更聚合，从逆向滞后形成等离子体蚀刻气体，并用由反向滞后蚀刻剂气体形成的等离子体蚀刻基于氧化硅的电介质层，从而比较宽的特征蚀刻更小的特征。

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