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    • 1. 发明申请
    • Pixel with variable resolution during exposure
    • 曝光期间可变分辨率的像素
    • US20050012968A1
    • 2005-01-20
    • US10619240
    • 2003-07-14
    • Nathaniel McCaffrey
    • Nathaniel McCaffrey
    • H01L27/148G06F15/00H04N1/04H04N5/235H04N5/30H04N5/335
    • H04N5/341
    • A variable resolution imager and method of forming output signals from a variable resolution imager are described. An imager having a number of pixels is provided. The variable resolution imager is accomplished by binning selected groups of pixels in various sections of the imager together, thereby forming regions of variable resolution. The larger the number of pixels binned together the lower the resolution of that section of the imager. The binning is controlled by programming signals to the imager so that the resolution can be changed within a frame or between frames. The resolution can be controlled by a computer processor or by an operator. Feedback of the output of the imager can be used to determine the resolution of various sections of the imager.
    • 描述了可变分辨率成像器和从可变分辨率成像器形成输出信号的方法。 提供了具有多个像素的成像器。 可变分辨率成像器通过将成像器的各个部分中的所选像素组合并在一起来实现,从而形成可变分辨率的区域。 合并在一起的像素数越多,该部分的分辨率越低。 分箱由编程信号控制到成像器,使得分辨率可以在帧内或帧之间改变。 该分辨率可由计算机处理器或操作者控制。 成像器输出的反馈可用于确定成像器各部分的分辨率。
    • 3. 发明申请
    • CMOS pixel with dual gate PMOS
    • 具有双栅极PMOS的CMOS像素
    • US20060278905A1
    • 2006-12-14
    • US11508354
    • 2006-08-23
    • Taner DosluogluNathaniel McCaffrey
    • Taner DosluogluNathaniel McCaffrey
    • H01L31/113
    • H01L27/14609H01L27/14632H01L27/14643H01L31/112
    • A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P+ type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N− well.
    • 具有双栅极PMOS的像素电路通过在N阱中形成两个P + +区形成。 N<>井是在P + +型衬底中。 两个P + SUP区域形成PMOS晶体管的源极和漏极。 形成在N阱内的PMOS晶体管不会影响光电荷的收集,只要PMOS晶体管的源极和漏极电位被设置在比N - 阱电位,使得它们相对于N 阱保持反向偏置。 用于形成源极和漏极区域的一个P + SUP区域可用于在读取该像素以准备下一个累积光电荷循环之后复位像素。 由于NΩ阱12的电位影响PMOS晶体管的沟道的导电性,因此N阱构成了双栅极PMOS晶体管的第二栅极。 添加两个NMOS晶体管使读出信号能够存储在NMOS晶体管之一的栅极处,从而使快照成像器成为可能。 该电路可以扩展以形成在N阱中共享一个共同漏极的两个PMOS晶体管。
    • 6. 发明申请
    • CMOS pixel with dual gate PMOS
    • 具有双栅极PMOS的CMOS像素
    • US20050156212A1
    • 2005-07-21
    • US11068283
    • 2005-02-28
    • Taner DosluogluNathaniel McCaffrey
    • Taner DosluogluNathaniel McCaffrey
    • H01L21/8238H01L27/092H01L27/146H01L29/10H01L29/76H01L31/036H01L31/10H01L31/112H01L31/113
    • H01L27/14609H01L27/14632H01L27/14643H01L31/112
    • A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N− well.
    • 具有双栅极PMOS的像素电路通过在N阱中形成两个P + +区形成。 N<> - 孔是在P + - SUP型衬底中。 两个P + SUP区域形成PMOS晶体管的源极和漏极。 形成在N阱内的PMOS晶体管不会影响光电荷的收集,只要PMOS晶体管的源极和漏极电位被设置在比N - 阱电位,使得它们相对于N 阱保持反向偏置。 用于形成源极和漏极区域的一个P + SUP区域可用于在读取该像素以准备下一个累积光电荷循环之后复位像素。 由于NΩ阱12的电位影响PMOS晶体管的沟道的导电性,因此N阱构成了双栅极PMOS晶体管的第二栅极。 添加两个NMOS晶体管使读出信号能够存储在NMOS晶体管之一的栅极处,从而使快照成像器成为可能。 该电路可以扩展以形成在N阱中共享一个共同漏极的两个PMOS晶体管。