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1. 发明授权

US07973686B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07973686B2
公开(公告)日：2011-07-05
申请号：US12688341
申请日：2010-01-15
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： H03M1/06
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0291 , G09G2320/0233
摘要： An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.
摘要翻译：集成电路装置包括多个数据线驱动电路，第一校正D / A转换电路和多个D / A转换电路。每个数据线驱动电路包括运算放大器，输入电容器和第一校正电容器。每个D / A转换电路将输出信号输出到输入电容器。第一校正D / A转换电路向第一校正电容器输出校正输出电压，以校正从数据线驱动器电路输出的数据信号。

2. 发明授权

US07768316B2 Decoder circuit, decoding method, output circuit, electro-optical device, and electronic instrument 有权
标题翻译：解码电路，解码方式，输出电路，电光装置和电子仪器
公开(公告)号：US07768316B2
公开(公告)日：2010-08-03
申请号：US12389938
申请日：2009-02-20
申请人： Yuichi Toriumi , Motoaki Nishimura , Takeshi Nomura
发明人： Yuichi Toriumi , Motoaki Nishimura , Takeshi Nomura
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.
摘要翻译：解码器电路包括：对（m + n）位地址信号的m位地址信号部分进行解码的第一解码器部分; 以及第二解码器部分，其对（m + n）位地址信号的n位地址信号部分进行解码，第一解码器部分包括第一AND运算电路部分，其输出指示m位解码结果的信号地址信号部分，以及输出指示m位地址信号部分的一部分的解码结果的信号的第二AND运算电路部分，第二解码器部分包括输出指示解码结果的信号的第三AND运算电路部分以及输出指示n位地址信号部分的一部分的解码结果的信号的第四AND运算电路部。

3. 发明申请

US20090160882A1 INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT 有权
标题翻译：集成电路装置，电光装置和电子仪器
公开(公告)号：US20090160882A1
公开(公告)日：2009-06-25
申请号：US12339742
申请日：2008-12-19
申请人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
发明人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
IPC分类号： G09G5/10 , G09G5/00
CPC分类号： G09G3/3685 , G09G3/2007 , G09G3/3696 , G09G2300/0426 , G09G2300/0857 , G09G2310/027 , G09G2310/0275 , G09G2310/0294 , G09G2330/028 , G09G2370/08
摘要： An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction,
摘要翻译：集成电路装置包括沿着第一方向布置的第一至第N存储块，电源电路和与第一至第N存储器块相对的第二方向的数据驱动器。电源电路包括输出模拟基准电源电压的模拟基准电源电压输出电路。模拟基准电源电压输出电路设置在第一至第N存储块之间的第M个存储块和第（M + 1）个存储器块之间。在数据驱动器的沿着第一方向的区域中提供模拟参考电源线，

4. 发明申请

US20090160849A1 INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT 审中-公开
标题翻译：集成电路装置，电光装置和电子仪器
公开(公告)号：US20090160849A1
公开(公告)日：2009-06-25
申请号：US12340025
申请日：2008-12-19
申请人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
发明人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
IPC分类号： G09G5/00
CPC分类号： G09G3/3685 , G09G3/2007 , G09G3/3696 , G09G2300/0426 , G09G2300/0857 , G09G2310/027 , G09G2310/0275 , G09G2310/0294 , G09G2330/028 , G09G2370/08
摘要： An integrated circuit device includes first to Nth data driver blocks that are disposed along a first direction. Each of the first to Nth data driver blocks includes first to Mth sub-driver blocks. Each of the sub-driver blocks includes a D/A conversion circuit that receives image data and D/A-converts the image data, and first to Lth data line driver circuits that are disposed along the first direction in a second direction with respect to the D/A conversion circuit and share the D/A conversion circuit.
摘要翻译：集成电路装置包括沿第一方向设置的第一至第N数据驱动器块。第一至第N数据驱动器块中的每一个包括第一至第M子驱动器块。每个子驱动器块包括接收图像数据并对图像数据进行D / A转换的D / A转换电路，以及第一至第L数据线驱动器电路，其相对于第二方向沿第一方向设置在第二方向上 D / A转换电路并共享D / A转换电路。

5. 发明申请

US20090096818A1 DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT 审中-公开
标题翻译：数据驱动器，集成电路器件和电子仪器
公开(公告)号：US20090096818A1
公开(公告)日：2009-04-16
申请号：US12251907
申请日：2008-10-15
申请人： Motoaki NISHIMURA , Chihiro SHIN , Haruo KAMIJO , Katsuhiko MAKI
发明人： Motoaki NISHIMURA , Chihiro SHIN , Haruo KAMIJO , Katsuhiko MAKI
IPC分类号： G06F3/038
CPC分类号： G09G3/3291 , G09G2310/0291 , G09G2310/0294
摘要： A data driver includes a D/A conversion circuit, a switch circuit, and a data line driver circuit. The switch circuit includes a first switch element provided between a first voltage output node of the D/A conversion circuit and a first input node of a grayscale generation amplifier, a second switch element that is provided between a second voltage output node of the D/A conversion circuit and the first input node and is exclusively turned ON/OFF with respect to the first switch element, a third switch element provided between the first voltage output node and a second input node, and a fourth switch element that is provided between the second voltage output node and the second input node and is exclusively turned ON/OFF with respect to the third switch element.
摘要翻译：数据驱动器包括D / A转换电路，开关电路和数据线驱动电路。开关电路包括设置在D / A转换电路的第一电压输出节点与灰阶发生放大器的第一输入节点之间的第一开关元件，设置在D / A转换电路的第二电压输出节点之间的第二开关元件， A转换电路和第一输入节点，并且相对于第一开关元件专门地接通/断开，设置在第一电压输出节点和第二输入节点之间的第三开关元件和设置在第一开关元件之间的第四开关元件第二电压输出节点和第二输入节点，并且相对于第三开关元件专门地接通/断开。

6. 发明申请

US20090009446A1 Driver circuit, electro-optical device, and electronic instrument 失效
标题翻译：驱动电路，电光装置和电子仪器
公开(公告)号：US20090009446A1
公开(公告)日：2009-01-08
申请号：US11902626
申请日：2007-09-24
申请人： Haruo Kamijo , Motoaki Nishimura , Takeshi Nomura
发明人： Haruo Kamijo , Motoaki Nishimura , Takeshi Nomura
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3688 , G09G2300/0426 , G09G2310/0248 , G09G2310/0297 , G09G2330/023 , H03F3/08
摘要： A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node.
摘要翻译：用于驱动电光装置的源极线的驱动器电路包括分别使第一和第二源极线短路的源极短路电路和源极短路节点，短路的源极电荷存储短路电路与源极电容器和源短路节点的一端连接的源电荷存储节点，向源电荷存储节点提供给定电压的电压设定电路和短路电路公共电极电压输出节点和源短路节点，电压输出到通过电光元件与像素电极相对设置的电光装置的公共电极施加到公共电极电压输出节点。

7. 发明授权

US07956833B2 Display driver, electro-optical device, and electronic instrument 有权
标题翻译：显示驱动器，电光器件和电子仪器
公开(公告)号：US07956833B2
公开(公告)日：2011-06-07
申请号：US11808901
申请日：2007-06-13
申请人： Satoru Ito , Hisanobu Ishiyama , Motoaki Nishimura , Kazuhiro Maekawa , Haruo Kamijo , Hironori Kobayashi , Isamu Moriya
发明人： Satoru Ito , Hisanobu Ishiyama , Motoaki Nishimura , Kazuhiro Maekawa , Haruo Kamijo , Hironori Kobayashi , Isamu Moriya
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3688 , G09G3/3696 , G09G2310/0248 , G09G2330/023
摘要： A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.
摘要翻译：显示驱动器包括公共电极电荷存储开关，其设置在可连接第一电容器元件的一端的第一电容器元件连接节点和与像素电极相对的公共电极的电压的公共电极电压输出节点之间提供通过电光材料的电光器件的源电荷存储开关，设置在可连接第二电容器元件的一端的第二电容器元件连接节点与源电压输出节点之间的电压存储开关，提供电光装置的源极线，以及设置在公共电极电压输出节点和源电压输出节点之间的节点短路开关。

8. 发明申请

US20100225511A1 INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT 有权
标题翻译：集成电路设备和电子仪器
公开(公告)号：US20100225511A1
公开(公告)日：2010-09-09
申请号：US12688341
申请日：2010-01-15
申请人： Motoaki NISHIMURA
发明人： Motoaki NISHIMURA
IPC分类号： H03M1/06 , H03M1/66
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0291 , G09G2320/0233
摘要： An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.
摘要翻译：集成电路装置包括多个数据线驱动电路，第一校正D / A转换电路和多个D / A转换电路。每个数据线驱动电路包括运算放大器，输入电容器和第一校正电容器。每个D / A转换电路将输出信号输出到输入电容器。第一校正D / A转换电路向第一校正电容器输出校正输出电压，以校正从数据线驱动器电路输出的数据信号。

9. 发明申请

US20050156924A1 Voltage booster circuit, power supply circuit, and liquid crystal driver 审中-公开
标题翻译：电压升压电路，电源电路和液晶驱动器
公开(公告)号：US20050156924A1
公开(公告)日：2005-07-21
申请号：US11024736
申请日：2004-12-30
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00 , H01L21/822 , H01L27/04 , H02J1/00 , H02M3/07
CPC分类号： G09G3/3611 , G09G3/3655 , G09G3/3685 , G09G3/3696 , G09G2310/06 , G09G2330/02
摘要： A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and first to fifth discharge transistors having one end connected to the system ground power supply voltage and the other end connected to the MOS transistors. The MOS transistors are implemented by a triple-well structure formed in a p-type semiconductor substrate. When a discharge operation is performed, the first to fifth discharge transistors are separately ON/OFF controlled, thereby preventing parasitic bipolar transistor elements from being Darlington-connected and preventing a current path from being formed.
摘要翻译：电荷泵电路包括：MOS晶体管串联连接并且具有供给系统接地电源电压的一端; 以及第一至第五放电晶体管，其一端连接到系统接地电源电压，另一端连接到MOS晶体管。 MOS晶体管通过形成在p型半导体衬底中的三阱结构来实现。当执行放电操作时，第一至第五放电晶体管分别被开/关控制，从而防止寄生双极晶体管元件达到达林顿连接并防止形成电流通路。

10. 发明授权

US08174475B2 D/A conversion circuit, data driver, integrated circuit device, and electronic instrument 有权
标题翻译： D / A转换电路，数据驱动器，集成电路器件和电子仪器
公开(公告)号：US08174475B2
公开(公告)日：2012-05-08
申请号：US12251865
申请日：2008-10-15
申请人： Motoaki Nishimura , Haruo Kamijo , Katsuhiko Maki
发明人： Motoaki Nishimura , Haruo Kamijo , Katsuhiko Maki
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G2300/0408 , G09G2310/0291
摘要： A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage.
摘要翻译： D / A转换电路包括分别输出第一电压和第二电压的第一D / A转换器和第二D / A转换器。第一D / A转换器的多个输入选择器中的第二双输入选择器基于输入数据选择（4i + 1）输入电压或第（4i + 3）输入电压，并输出所选择的输入电压到后续阶段中的选择器块的选择器。第二D / A转换器的多个三输入选择器中的第三个三输入选择器基于第二输入选择器选择第四输入电压，第（4i + 2）输入电压或第（4i + 4）输入电压，输入数据，并将选择的输入电压输出到下一级的选择器块的选择器。

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