专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07973686B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07973686B2
公开(公告)日：2011-07-05
申请号：US12688341
申请日：2010-01-15
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： H03M1/06
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0291 , G09G2320/0233
摘要： An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.
摘要翻译：集成电路装置包括多个数据线驱动电路，第一校正D / A转换电路和多个D / A转换电路。每个数据线驱动电路包括运算放大器，输入电容器和第一校正电容器。每个D / A转换电路将输出信号输出到输入电容器。第一校正D / A转换电路向第一校正电容器输出校正输出电压，以校正从数据线驱动器电路输出的数据信号。

2. 发明授权

US07768316B2 Decoder circuit, decoding method, output circuit, electro-optical device, and electronic instrument 有权
标题翻译：解码电路，解码方式，输出电路，电光装置和电子仪器
公开(公告)号：US07768316B2
公开(公告)日：2010-08-03
申请号：US12389938
申请日：2009-02-20
申请人： Yuichi Toriumi , Motoaki Nishimura , Takeshi Nomura
发明人： Yuichi Toriumi , Motoaki Nishimura , Takeshi Nomura
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.
摘要翻译：解码器电路包括：对（m + n）位地址信号的m位地址信号部分进行解码的第一解码器部分; 以及第二解码器部分，其对（m + n）位地址信号的n位地址信号部分进行解码，第一解码器部分包括第一AND运算电路部分，其输出指示m位解码结果的信号地址信号部分，以及输出指示m位地址信号部分的一部分的解码结果的信号的第二AND运算电路部分，第二解码器部分包括输出指示解码结果的信号的第三AND运算电路部分以及输出指示n位地址信号部分的一部分的解码结果的信号的第四AND运算电路部。

3. 发明申请

US20090009446A1 Driver circuit, electro-optical device, and electronic instrument 失效
标题翻译：驱动电路，电光装置和电子仪器
公开(公告)号：US20090009446A1
公开(公告)日：2009-01-08
申请号：US11902626
申请日：2007-09-24
申请人： Haruo Kamijo , Motoaki Nishimura , Takeshi Nomura
发明人： Haruo Kamijo , Motoaki Nishimura , Takeshi Nomura
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3688 , G09G2300/0426 , G09G2310/0248 , G09G2310/0297 , G09G2330/023 , H03F3/08
摘要： A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node.
摘要翻译：用于驱动电光装置的源极线的驱动器电路包括分别使第一和第二源极线短路的源极短路电路和源极短路节点，短路的源极电荷存储短路电路与源极电容器和源短路节点的一端连接的源电荷存储节点，向源电荷存储节点提供给定电压的电压设定电路和短路电路公共电极电压输出节点和源短路节点，电压输出到通过电光元件与像素电极相对设置的电光装置的公共电极施加到公共电极电压输出节点。

4. 发明授权

US07956833B2 Display driver, electro-optical device, and electronic instrument 有权
标题翻译：显示驱动器，电光器件和电子仪器
公开(公告)号：US07956833B2
公开(公告)日：2011-06-07
申请号：US11808901
申请日：2007-06-13
申请人： Satoru Ito , Hisanobu Ishiyama , Motoaki Nishimura , Kazuhiro Maekawa , Haruo Kamijo , Hironori Kobayashi , Isamu Moriya
发明人： Satoru Ito , Hisanobu Ishiyama , Motoaki Nishimura , Kazuhiro Maekawa , Haruo Kamijo , Hironori Kobayashi , Isamu Moriya
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3688 , G09G3/3696 , G09G2310/0248 , G09G2330/023
摘要： A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.
摘要翻译：显示驱动器包括公共电极电荷存储开关，其设置在可连接第一电容器元件的一端的第一电容器元件连接节点和与像素电极相对的公共电极的电压的公共电极电压输出节点之间提供通过电光材料的电光器件的源电荷存储开关，设置在可连接第二电容器元件的一端的第二电容器元件连接节点与源电压输出节点之间的电压存储开关，提供电光装置的源极线，以及设置在公共电极电压输出节点和源电压输出节点之间的节点短路开关。

5. 发明申请

US20050156924A1 Voltage booster circuit, power supply circuit, and liquid crystal driver 审中-公开
标题翻译：电压升压电路，电源电路和液晶驱动器
公开(公告)号：US20050156924A1
公开(公告)日：2005-07-21
申请号：US11024736
申请日：2004-12-30
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G09G5/00 , H01L21/822 , H01L27/04 , H02J1/00 , H02M3/07
CPC分类号： G09G3/3611 , G09G3/3655 , G09G3/3685 , G09G3/3696 , G09G2310/06 , G09G2330/02
摘要： A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and first to fifth discharge transistors having one end connected to the system ground power supply voltage and the other end connected to the MOS transistors. The MOS transistors are implemented by a triple-well structure formed in a p-type semiconductor substrate. When a discharge operation is performed, the first to fifth discharge transistors are separately ON/OFF controlled, thereby preventing parasitic bipolar transistor elements from being Darlington-connected and preventing a current path from being formed.
摘要翻译：电荷泵电路包括：MOS晶体管串联连接并且具有供给系统接地电源电压的一端; 以及第一至第五放电晶体管，其一端连接到系统接地电源电压，另一端连接到MOS晶体管。 MOS晶体管通过形成在p型半导体衬底中的三阱结构来实现。当执行放电操作时，第一至第五放电晶体管分别被开/关控制，从而防止寄生双极晶体管元件达到达林顿连接并防止形成电流通路。

6. 发明授权

US08576257B2 Integrated circuit device, electro-optical device, and electronic instrument 有权
标题翻译：集成电路器件，电光器件和电子仪器
公开(公告)号：US08576257B2
公开(公告)日：2013-11-05
申请号：US12339742
申请日：2008-12-19
申请人： Hiroshi Kiya , Chihiro Shin , Haruo Kamijo , Motoaki Nishimura , Katsuhiko Maki
发明人： Hiroshi Kiya , Chihiro Shin , Haruo Kamijo , Motoaki Nishimura , Katsuhiko Maki
IPC分类号： G09G5/10
CPC分类号： G09G3/3685 , G09G3/2007 , G09G3/3696 , G09G2300/0426 , G09G2300/0857 , G09G2310/027 , G09G2310/0275 , G09G2310/0294 , G09G2330/028 , G09G2370/08
摘要： An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction.
摘要翻译：集成电路装置包括沿着第一方向布置的第一至第N存储块，电源电路和与第一至第N存储器块相对的第二方向的数据驱动器。电源电路包括输出模拟基准电源电压的模拟基准电源电压输出电路。模拟基准电源电压输出电路设置在第一至第N存储块之间的第M个存储块和第（M + 1）个存储器块之间。在数据驱动器的沿着第一方向的区域中提供模拟参考电源线。

7. 发明授权

US07723799B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07723799B2
公开(公告)日：2010-05-25
申请号：US12017570
申请日：2008-01-22
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： H01L29/76 , H01L29/94 , H01L23/62
CPC分类号： H01L27/0921
摘要： A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a conductive state brought by a gate substantially connected to the ground voltage to maintain the low voltage to be substantially at the ground voltage until a possibility that the low voltage rises higher than the ground voltage is eliminated.
摘要翻译：半导体器件包括P衬底，设置在P衬底中的N阱，设置在P衬底中并且具有连接到接地电压的源极和漏极之一的NMOS晶体管，设置在P衬底中的P阱 P基板并连接到低电压，以便将低电压的P基板提供为低于接地电压; PMOS晶体管，其设置在N阱中并且具有连接到电源电压的源极， N抽头设置在N阱中并连接到电源电压，以便为N阱提供电源电压;以及凹陷型PMOS晶体管，其漏极连接到低电压并且源极连接以防止在PMOS晶体管，N阱，NMOS晶体管和P基板之间存在的寄生晶体管因电源电压和地电压之间的闭锁而导致低电压上升高于接地电压，a d用于由基本连接到接地电压的栅极引起的导通状态，以将低电压基本上保持在接地电压，直到低电压上升高于接地电压的可能性被消除。

8. 发明申请

US20080084408A1 Gate driver, electro-optical device, electronic instrument, and drive method 审中-公开
标题翻译：门驱动器，电光器件，电子仪器和驱动方法
公开(公告)号：US20080084408A1
公开(公告)日：2008-04-10
申请号：US11907216
申请日：2007-10-10
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3677 , G09G2330/021
摘要： A gate driver includes a first gate output circuit which outputs a select signal for selecting the first gate line, a second gate output circuit which outputs a select signal for selecting the second gate line in a select period subsequent to the select period of the first gate line, and a transistor as a first gate line short-circuiting circuit provided between outputs of the first and second gate output circuits. The transistor short-circuits the outputs of the first and second gate output circuits in a period between the select period of the first gate line and the select period of the second gate line.
摘要翻译：栅极驱动器包括输出用于选择第一栅极线的选择信号的第一栅极输出电路，在第一栅极的选择周期之后的选择周期中输出用于选择第二栅极线的选择信号的第二栅极输出电路以及设置在第一和第二栅极输出电路的输出之间的作为第一栅极线短路电路的晶体管。晶体管在第一栅极线的选择周期和第二栅极线的选择周期之间的周期内短路第一和第二栅极输出电路的输出。

9. 发明申请

US20080001876A1 Display driver, electro-optical device, and electronic instrument 有权
标题翻译：显示驱动器，电光器件和电子仪器
公开(公告)号：US20080001876A1
公开(公告)日：2008-01-03
申请号：US11808901
申请日：2007-06-13
申请人： Satoru Ito , Hisanobu Ishiyama , Motoaki Nishimura , Kazuhiro Maekawa , Haruo Kamijo , Hironori Kobayashi , Isamu Moriya
发明人： Satoru Ito , Hisanobu Ishiyama , Motoaki Nishimura , Kazuhiro Maekawa , Haruo Kamijo , Hironori Kobayashi , Isamu Moriya
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3688 , G09G3/3696 , G09G2310/0248 , G09G2330/023
摘要： A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.
摘要翻译：显示驱动器包括公共电极电荷存储开关，其设置在可连接第一电容器元件的一端的第一电容器元件连接节点和与像素电极相对的公共电极的电压的公共电极电压输出节点之间提供通过电光材料的电光器件的源电荷存储开关，设置在可连接第二电容器元件的一端的第二电容器元件连接节点与源电压输出节点之间的电压存储开关，提供电光装置的源极线，以及设置在公共电极电压输出节点和源电压输出节点之间的节点短路开关。

10. 发明授权

US07295198B2 Voltage booster circuit, power supply circuit, and liquid crystal driver 有权
标题翻译：电压升压电路，电源电路和液晶驱动器
公开(公告)号：US07295198B2
公开(公告)日：2007-11-13
申请号：US11024713
申请日：2004-12-30
申请人： Motoaki Nishimura
发明人： Motoaki Nishimura
IPC分类号： G09G5/00
CPC分类号： G09G3/3611 , G09G3/3685 , G09G3/3696 , G09G2310/06 , G09G2330/02
摘要： A charge-pump circuit includes: MOS transistors connected in series and having one end to which a system ground power supply voltage is supplied; and a discharge transistor. The discharge transistor has one end connected to a node which is connected to the MOS transistors, and the system ground power supply voltage is supplied to the other end of the discharge transistor. The MOS transistors are implemented by a triple-well structure formed in a p-type semiconductor substrate. When a normal operation is performed, the MOS transistors are turned ON and the discharge transistor is turned OFF. When a discharge operation is performed, the MOS transistors are turned OFF and the discharge transistor is turned ON, and a current path is formed by parasitic bipolar transistor elements.
摘要翻译：电荷泵电路包括：MOS晶体管串联连接并且具有供给系统接地电源电压的一端; 和放电晶体管。放电晶体管的一端连接到连接到MOS晶体管的节点，并且系统地电源电压被提供给放电晶体管的另一端。 MOS晶体管通过形成在p型半导体衬底中的三阱结构来实现。当执行正常操作时，MOS晶体管导通，放电晶体管截止。当执行放电操作时，MOS晶体管截止并且放电晶体管导通，并且电流路径由寄生双极晶体管元件形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式