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1. 发明申请

US20090160881A1 INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT 审中-公开
标题翻译：集成电路装置，电光装置和电子仪器
公开(公告)号：US20090160881A1
公开(公告)日：2009-06-25
申请号：US12339498
申请日：2008-12-19
申请人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
发明人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
IPC分类号： G06F3/038
CPC分类号： G09G3/3611 , G09G3/3648 , G09G3/3688 , G09G2310/027 , G09G2310/0291 , G09G2360/18
摘要： An integrated circuit device includes first to Nth memory blocks that are disposed along a first direction, and first to Nth data driver blocks that are disposed along the first direction in a second direction with respect to the first to Nth memory blocks. A Jth memory block among the first to Nth memory blocks dot-sequentially reads subpixel image data and outputs the subpixel image data to a corresponding Jth data driver block among the first to Nth data driver blocks, the subpixel image data being image data corresponding to at least one subpixel. The Jth data driver block receives the subpixel image data from the Jth memory block, and outputs a data signal corresponding to the subpixel image data.
摘要翻译：集成电路装置包括沿着第一方向设置的第一至第N存储器块以及相对于第一至第N存储器块沿第二方向沿着第一方向布置的第一至第N数据驱动器块。第一至第N存储器块中的第J个存储器块按顺序读取子像素图像数据，并将子像素图像数据输出到第一至第N数据驱动器块中的对应的第J个数据驱动器块，子像素图像数据是对应于至少一个子像素。第j个数据驱动块从第j个存储块接收子像素图像数据，并输出与子像素图像数据对应的数据信号。

2. 发明申请

US20090160882A1 INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT 有权
标题翻译：集成电路装置，电光装置和电子仪器
公开(公告)号：US20090160882A1
公开(公告)日：2009-06-25
申请号：US12339742
申请日：2008-12-19
申请人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
发明人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
IPC分类号： G09G5/10 , G09G5/00
CPC分类号： G09G3/3685 , G09G3/2007 , G09G3/3696 , G09G2300/0426 , G09G2300/0857 , G09G2310/027 , G09G2310/0275 , G09G2310/0294 , G09G2330/028 , G09G2370/08
摘要： An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction,
摘要翻译：集成电路装置包括沿着第一方向布置的第一至第N存储块，电源电路和与第一至第N存储器块相对的第二方向的数据驱动器。电源电路包括输出模拟基准电源电压的模拟基准电源电压输出电路。模拟基准电源电压输出电路设置在第一至第N存储块之间的第M个存储块和第（M + 1）个存储器块之间。在数据驱动器的沿着第一方向的区域中提供模拟参考电源线，

3. 发明申请

US20090160849A1 INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT 审中-公开
标题翻译：集成电路装置，电光装置和电子仪器
公开(公告)号：US20090160849A1
公开(公告)日：2009-06-25
申请号：US12340025
申请日：2008-12-19
申请人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
发明人： Hiroshi KIYA , Chihiro SHIN , Haruo KAMIJO , Motoaki NISHIMURA , Katsuhiko MAKI
IPC分类号： G09G5/00
CPC分类号： G09G3/3685 , G09G3/2007 , G09G3/3696 , G09G2300/0426 , G09G2300/0857 , G09G2310/027 , G09G2310/0275 , G09G2310/0294 , G09G2330/028 , G09G2370/08
摘要： An integrated circuit device includes first to Nth data driver blocks that are disposed along a first direction. Each of the first to Nth data driver blocks includes first to Mth sub-driver blocks. Each of the sub-driver blocks includes a D/A conversion circuit that receives image data and D/A-converts the image data, and first to Lth data line driver circuits that are disposed along the first direction in a second direction with respect to the D/A conversion circuit and share the D/A conversion circuit.
摘要翻译：集成电路装置包括沿第一方向设置的第一至第N数据驱动器块。第一至第N数据驱动器块中的每一个包括第一至第M子驱动器块。每个子驱动器块包括接收图像数据并对图像数据进行D / A转换的D / A转换电路，以及第一至第L数据线驱动器电路，其相对于第二方向沿第一方向设置在第二方向上 D / A转换电路并共享D / A转换电路。

4. 发明申请

US20090096818A1 DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT 审中-公开
标题翻译：数据驱动器，集成电路器件和电子仪器
公开(公告)号：US20090096818A1
公开(公告)日：2009-04-16
申请号：US12251907
申请日：2008-10-15
申请人： Motoaki NISHIMURA , Chihiro SHIN , Haruo KAMIJO , Katsuhiko MAKI
发明人： Motoaki NISHIMURA , Chihiro SHIN , Haruo KAMIJO , Katsuhiko MAKI
IPC分类号： G06F3/038
CPC分类号： G09G3/3291 , G09G2310/0291 , G09G2310/0294
摘要： A data driver includes a D/A conversion circuit, a switch circuit, and a data line driver circuit. The switch circuit includes a first switch element provided between a first voltage output node of the D/A conversion circuit and a first input node of a grayscale generation amplifier, a second switch element that is provided between a second voltage output node of the D/A conversion circuit and the first input node and is exclusively turned ON/OFF with respect to the first switch element, a third switch element provided between the first voltage output node and a second input node, and a fourth switch element that is provided between the second voltage output node and the second input node and is exclusively turned ON/OFF with respect to the third switch element.
摘要翻译：数据驱动器包括D / A转换电路，开关电路和数据线驱动电路。开关电路包括设置在D / A转换电路的第一电压输出节点与灰阶发生放大器的第一输入节点之间的第一开关元件，设置在D / A转换电路的第二电压输出节点之间的第二开关元件， A转换电路和第一输入节点，并且相对于第一开关元件专门地接通/断开，设置在第一电压输出节点和第二输入节点之间的第三开关元件和设置在第一开关元件之间的第四开关元件第二电压输出节点和第二输入节点，并且相对于第三开关元件专门地接通/断开。

5. 发明申请

US20090096817A1 D/A CONVERSION CIRCUIT, DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT 有权
标题翻译： D / A转换电路，数据驱动器，集成电路设备和电子仪器
公开(公告)号：US20090096817A1
公开(公告)日：2009-04-16
申请号：US12251865
申请日：2008-10-15
申请人： Motoaki NISHIMURA , Haruo KAMIJO , Katsuhiko MAKI
发明人： Motoaki NISHIMURA , Haruo KAMIJO , Katsuhiko MAKI
IPC分类号： G09G5/10
CPC分类号： G09G3/3696 , G09G2300/0408 , G09G2310/0291
摘要： A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage.
摘要翻译： D / A转换电路包括分别输出第一电压和第二电压的第一D / A转换器和第二D / A转换器。第一D / A转换器的多个输入选择器中的第二双输入选择器基于输入数据选择（4i + 1）输入电压或第（4i + 3）输入电压，并输出所选择的输入电压到后续阶段中的选择器块的选择器。第二D / A转换器的多个三输入选择器中的第三个三输入选择器基于第二输入选择器选择第四输入电压，第（4i + 2）输入电压或第（4i + 4）输入电压，输入数据，并将选择的输入电压输出到下一级的选择器块的选择器。

6. 发明申请

US20080204123A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080204123A1
公开(公告)日：2008-08-28
申请号：US12017570
申请日：2008-01-22
申请人： Motoaki NISHIMURA
发明人： Motoaki NISHIMURA
IPC分类号： G05F1/10
CPC分类号： H01L27/0921
摘要： A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the P-substrate with the low voltage to be lower than the ground voltage, a PMOS transistor disposed in the N-well and having a source connected to a power supply voltage, an N-tap disposed in the N-well and connected to the power supply voltage so as to provide the N-well with the power supply voltage, and a depression-type PMOS transistor having a drain connected to the low voltage and a source connected to the ground voltage so as to prevent a parasitic transistor, which may exist among the PMOS transistor, the N-well, the NMOS transistor, and the P-substrate, from causing a latchup between the power supply voltage and the ground voltage due to the low voltage rising higher than the ground voltage, and for becoming in a conductive state brought by a gate substantially connected to the ground voltage to maintain the low voltage to be substantially at the ground voltage until a possibility that the low voltage rises higher than the ground voltage is eliminated.
摘要翻译：半导体器件包括P衬底，设置在P衬底中的N阱，设置在P衬底中并且具有连接到接地电压的源极和漏极之一的NMOS晶体管，设置在P衬底中的P阱 P基板并连接到低电压，以便将低电压的P基板提供为低于接地电压; PMOS晶体管，其设置在N阱中并且具有连接到电源电压的源极， N抽头设置在N阱中并连接到电源电压，以便为N阱提供电源电压;以及凹陷型PMOS晶体管，其漏极连接到低电压并且源极连接以防止在PMOS晶体管，N阱，NMOS晶体管和P基板之间存在的寄生晶体管因电源电压和地电压之间的闭锁而导致低电压上升高于接地电压，a d用于由基本连接到接地电压的栅极引起的导通状态，以将低电压基本上保持在接地电压，直到低电压上升高于接地电压的可能性被消除。

7. 发明申请

US20100225676A1 INTEGRATED CIRCUIT DEVICE, ELECTRO OPTICAL DEVICE AND ELECTRONIC APPARATUS 审中-公开
标题翻译：集成电路装置，电光装置和电子装置
公开(公告)号：US20100225676A1
公开(公告)日：2010-09-09
申请号：US12713458
申请日：2010-02-26
申请人： Motoaki NISHIMURA
发明人： Motoaki NISHIMURA
IPC分类号： G06F3/038 , G09G5/10
CPC分类号： G09G3/3688 , G09G3/3696 , G09G2310/0291 , G09G2330/021
摘要： An integrated circuit device includes: a grayscale voltage generation circuit that outputs a plurality of grayscale voltages; and a plurality of driver circuits that drive a plurality of data lines upon receiving the plurality of grayscale voltages, wherein the grayscale voltage generation circuit voltage-divides between a high voltage side power supply voltage and a ground voltage thereby generating the plurality of grayscale voltages, each of the plurality of driver circuits includes a data line driving circuit having a first capacitor and a second capacitor, wherein the data line driving circuit performs an inversion-amplification of a gain according to a capacitor ratio between the first capacitor and the second capacitor, thereby outputting data voltages in an output range whose lower limit voltage is higher than the ground voltage.
摘要翻译：集成电路装置包括：输出多个灰度级电压的灰阶电压产生电路; 以及多个驱动电路，其在接收到所述多个灰度电压时驱动多条数据线，其中所述灰度级电压产生电路电压在高压侧电源电压和接地电压之间分压，由此产生所述多个灰度电压，所述多个驱动电路中的每一个包括具有第一电容器和第二电容器的数据线驱动电路，其中所述数据线驱动电路根据所述第一电容器和所述第二电容器之间的电容器比进行增益的反相放大，从而在下限电压高于接地电压的输出范围内输出数据电压。

8. 发明申请

US20090212820A1 DECODER CIRCUIT, DECODING METHOD, OUTPUT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT 有权
标题翻译：解码器电路，解码方法，输出电路，电光设备和电子仪器
公开(公告)号：US20090212820A1
公开(公告)日：2009-08-27
申请号：US12389938
申请日：2009-02-20
申请人： Yuichi TORIUMI , Motoaki NISHIMURA , Takeshi NOMURA
发明人： Yuichi TORIUMI , Motoaki NISHIMURA , Takeshi NOMURA
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.
摘要翻译：解码器电路包括：对（m + n）位地址信号的m位地址信号部分进行解码的第一解码器部分; 以及第二解码器部分，其对（m + n）位地址信号的n位地址信号部分进行解码，第一解码器部分包括第一AND运算电路部分，其输出指示m位解码结果的信号地址信号部分，以及输出指示m位地址信号部分的一部分的解码结果的信号的第二AND运算电路部分，第二解码器部分包括输出指示解码结果的信号的第三AND运算电路部分以及输出指示n位地址信号部分的一部分的解码结果的信号的第四AND运算电路部。

9. 发明申请

US20090096491A1 DRIVER CIRCUIT, DATA DRIVER, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC INSTRUMENT 审中-公开
标题翻译：驱动电路，数据驱动器，集成电路设备和电子仪器
公开(公告)号：US20090096491A1
公开(公告)日：2009-04-16
申请号：US12250934
申请日：2008-10-14
申请人： Motoaki NISHIMURA
发明人： Motoaki NISHIMURA
IPC分类号： H03K3/00
CPC分类号： H03K5/249 , G09G3/3688 , G09G2310/027 , H03F3/45475 , H03F2203/45514 , H03F2203/45551
摘要： A driver circuit includes a first capacitor provided between a first node and a reference node, a second capacitor provided between a second node and the reference node, a first switch element provided between the first node and an input node, a second switch element provided between the first node and an analog reference power supply, a third switch element provided between the second node and an output node, a fourth switch element provided between the second node and the analog reference power supply, and a fifth switch element provided between the output node and the reference node. A first capacitor area and a second capacitor area are disposed along a first direction. The first switch element and the second switch element are disposed in a third direction with respect to the first capacitor area and the second capacitor area. The third switch element and the fourth switch element are disposed in the first direction with respect to the first capacitor area and the second capacitor area. A reference node line is provided in a second direction with respect to the first switch element, the second switch element, the third switch element, and the fourth switch element.
摘要翻译：驱动器电路包括设置在第一节点和参考节点之间的第一电容器，设置在第二节点和参考节点之间的第二电容器，设置在第一节点和输入节点之间的第一开关元件，第一节点和模拟参考电源，设置在第二节点和输出节点之间的第三开关元件，设置在第二节点和模拟参考电源之间的第四开关元件，以及设置在输出节点之间的第五开关元件和参考节点。第一电容器区域和第二电容器区域沿第一方向设置。第一开关元件和第二开关元件相对于第一电容器区域和第二电容器区域设置在第三方向上。第三开关元件和第四开关元件相对于第一电容器区域和第二电容器区域设置在第一方向上。参考节点线相对于第一开关元件，第二开关元件，第三开关元件和第四开关元件在第二方向上设置。

10. 发明申请

US20100225511A1 INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT 有权
标题翻译：集成电路设备和电子仪器
公开(公告)号：US20100225511A1
公开(公告)日：2010-09-09
申请号：US12688341
申请日：2010-01-15
申请人： Motoaki NISHIMURA
发明人： Motoaki NISHIMURA
IPC分类号： H03M1/06 , H03M1/66
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0291 , G09G2320/0233
摘要： An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.
摘要翻译：集成电路装置包括多个数据线驱动电路，第一校正D / A转换电路和多个D / A转换电路。每个数据线驱动电路包括运算放大器，输入电容器和第一校正电容器。每个D / A转换电路将输出信号输出到输入电容器。第一校正D / A转换电路向第一校正电容器输出校正输出电压，以校正从数据线驱动器电路输出的数据信号。

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