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1. 发明授权

US08785272B2 Process to make high-K transistor dielectrics 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US08785272B2
公开(公告)日：2014-07-22
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

2. 发明申请

US20080083248A1 Bead ornament structure 审中-公开
标题翻译：珠饰品结构
公开(公告)号：US20080083248A1
公开(公告)日：2008-04-10
申请号：US11544558
申请日：2006-10-10
申请人： Ming-Fang Wang , Hsueh-Hu Chiang
发明人： Ming-Fang Wang , Hsueh-Hu Chiang
IPC分类号： A44C25/00
CPC分类号： A44C25/001
摘要： The present invention discloses a bead ornament structure that includes: two half bead bodies, each having a level attaching surface and a protruding external surface protruded from the attaching surface; and a partition base having a level surface disposed on two lateral bases of the partition base, each having a circular flange extended around a section of the partition base, such that the two half bead bodies are embedded into the circular flange with an appropriate tightness by the level attaching surface and attached onto the base, and the periphery of the two half bead bodies is bound and fixed by the circular flange extended from the partition base.
摘要翻译：本发明公开了一种珠饰装饰结构，其包括：两个半珠体，每个具有从安装表面突出的水平安装表面和突出的外表面; 以及分隔基部，其具有设置在所述分隔基部的两个侧面基部上的水平面，每个隔壁具有围绕所述分隔基部的一部分延伸的圆形凸缘，使得所述两个半胎圈体以适当的紧密度被嵌入所述圆形凸缘中水平安装表面并附接到基座上，并且两个半胎边体的周边通过从分隔基部延伸的圆形凸缘而被固定和固定。

3. 发明授权

US07303996B2 High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics 有权
标题翻译：高K栅极电介质叠层等离子体处理来调节阈值电压特性
公开(公告)号：US07303996B2
公开(公告)日：2007-12-04
申请号：US10677158
申请日：2003-10-01
申请人： Ming-Fang Wang , Tuo-Hung Hou , Kai-Lin Mai , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Tuo-Hung Hou , Kai-Lin Mai , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/28185 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.
摘要翻译：一种用于处理包括高K栅极电介质堆叠的栅极结构以改善电性能特性的方法，包括在硅衬底上提供包括二元氧化物的栅极介电层堆叠; 在所述栅极介电层堆叠上形成多晶硅层; 光刻图案化和蚀刻以形成栅极结构; 以及进行至少一种栅极结构的等离子体处理，所述栅极结构包括选自H 2，N 2，O 2， / SUB>和NH 3。

4. 发明申请

US20050196927A1 Process for integration of a high dielectric constant gate insulator layer in a CMOS device 有权
公开(公告)号：US20050196927A1
公开(公告)日：2005-09-08
申请号：US11119951
申请日：2005-05-02
申请人： Ming-Fang Wang , Chien-Hao Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Chien-Hao Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L29/665 , Y10S257/90
摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

5. 发明申请

US20050074978A1 High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics 有权
标题翻译：高K栅极电介质叠层等离子体处理来调节阈值电压特性
公开(公告)号：US20050074978A1
公开(公告)日：2005-04-07
申请号：US10677158
申请日：2003-10-01
申请人： Ming-Fang Wang , Tuo-Hung Hou , Kai-Lin Mai , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Tuo-Hung Hou , Kai-Lin Mai , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L29/51 , H01L29/78 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28185 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.
摘要翻译：一种用于处理包括高K栅极电介质堆叠的栅极结构以改善电性能特性的方法，包括在硅衬底上提供包括二元氧化物的栅极介电层堆叠; 在所述栅极介电层堆叠上形成多晶硅层; 光刻图案化和蚀刻以形成栅极结构; 以及进行包括选自H 2，N 2，O 2和NH 3的等离子体源气体的栅极结构的至少一个等离子体处理。

6. 发明申请

US20050056900A1 Method and structure for forming high-k gates 失效
标题翻译：用于形成高k门的方法和结构
公开(公告)号：US20050056900A1
公开(公告)日：2005-03-17
申请号：US10662845
申请日：2003-09-15
申请人： Ming-Fang Wang , Chia-Lin Chen , Chih-Wei Yang , Chi-Chun Chen , Tuo-Hung Hou , Yeou-Ming Lin , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Chia-Lin Chen , Chih-Wei Yang , Chi-Chun Chen , Tuo-Hung Hou , Yeou-Ming Lin , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/28 , H01L21/314 , H01L29/51 , H01L29/76
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L29/513
摘要： A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.
摘要翻译：一种用于形成在栅极结构形成工艺中具有改进的电性能的改进的栅极堆叠结构的方法用于形成高介电常数栅极结构的方法，包括提供包括暴露表面部分的硅衬底; 在暴露的表面部分上形成具有小于约10埃的厚度的界面层; 在介电常数大于约10的界面层上形成高介电常数金属氧化物层; 在高介电常数金属氧化物层上形成阻挡层; 在阻挡层上形成电极层; 并且根据蚀刻图案通过电极层，阻挡层，高介电常数材料层和界面层的厚度进行蚀刻，以形成高介电常数栅极结构。

7. 发明授权

US06706581B1 Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices 失效
标题翻译：双栅电介质方案：用于高性能器件的SiON和低功率器件的高k
公开(公告)号：US06706581B1
公开(公告)日：2004-03-16
申请号：US10282387
申请日：2002-10-29
申请人： Tou-Hung Hou , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Shih-Chang Chen
发明人： Tou-Hung Hou , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L218238
CPC分类号： H01L21/823456 , H01L21/823462
摘要： A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT
摘要翻译：描述了可扩展以满足对于50nm和70nm技术节点的要求的形成双栅极电介质层的方法。衬底具有分离器件区域的STI区域。界面层和高k电介质层依次沉积在衬底上。在一个器件区域上去除两个层，并且在暴露的器件区域上生长具有EOT <10nm的超薄氮氧化硅层。在SiON介电层的生长期间，高k电介质层退火。高k电介质层由金属氧化物或其硅酸盐或铝酸盐形成，并且能够以具有抑制的漏电流的EOT <1.8nm制造低功率器件。当形成多个栅极时，该方法与双重或三重氧化物厚度工艺兼容。

8. 发明授权

US06656764B1 Process for integration of a high dielectric constant gate insulator layer in a CMOS device 有权
标题翻译：在CMOS器件中集成高介电常数栅极绝缘体层的工艺
公开(公告)号：US06656764B1
公开(公告)日：2003-12-02
申请号：US10146287
申请日：2002-05-15
申请人： Ming-Fang Wang , Chien-Hao Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Chien-Hao Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L2100
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L29/665 , Y10S257/90
摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.
摘要翻译：已经开发了CMOS器件结构，以及制造具有由高k金属氧化物层构成的栅极绝缘体层的CMOS器件的方法。在沉积高k金属氧化物层之前，该工艺特征是形成凹陷的，重掺杂的源极/漏极区域以及垂直的多晶硅LDD间隔物。先前用作凹陷区域的掩模的氮化硅形状的去除，其又用于重掺杂源极/漏极区域的适应，提供了由高k金属氧化物层占据的空间。通过延迟沉积金属氧化物层，在高温下进行保存，通过垂直多晶硅间隔物对接的高k栅极绝缘体层的完整性，并覆盖由半导体衬底的非凹陷部分提供的沟道区域退火如重掺杂源极/漏极区的激活退火，以及用于金属硅化物形成的退火。

9. 发明申请

US20110318915A1 PROCESS TO MAKE HIGH-K TRANSISTOR DIELECTRICS 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US20110318915A1
公开(公告)日：2011-12-29
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

10. 发明授权

US07351994B2 Noble high-k device 有权
标题翻译：高贵的高k设备
公开(公告)号：US07351994B2
公开(公告)日：2008-04-01
申请号：US10762164
申请日：2004-01-21
申请人： Liang-Gi Yao , Tien-Chih Chang , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Tien-Chih Chang , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/517 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.
摘要翻译：至少一个高k装置和用于形成至少一个高k装置的方法包括以下。具有在其上形成的应变衬底的结构。应变衬底包括至少最上层的应变Si外延层。在应变衬底上的至少一个电介质栅极氧化物部分。所述至少一个电介质栅极氧化物部分具有大于约4.0的介电常数。在所述至少一个电介质栅极氧化物部分中的每一个上方的器件，以完成所述至少一个高k器件。一种形成所述至少一个高k装置的方法。

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