专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08250322B2 Command reordering based on command priority 有权
标题翻译：基于命令优先级的命令重新排序
公开(公告)号：US08250322B2
公开(公告)日：2012-08-21
申请号：US12635828
申请日：2009-12-11
申请人： Ming Chuan Huang , Chia Hao Lee , Han Liang Chou
发明人： Ming Chuan Huang , Chia Hao Lee , Han Liang Chou
IPC分类号： G06F13/18
CPC分类号： G06F12/0607 , G06F13/1626
摘要： A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.
摘要翻译：用于存储器访问的控制系统包括系统存储器访问命令缓冲器，存储器访问命令并行处理器，DRAM命令控制器和读取数据缓冲器。系统存储器访问命令缓冲器存储多个系统存储器访问命令。存储器访问命令并行处理器连接到系统存储器访问命令缓冲器，用于将系统存储器访问命令读取和解码为多个DRAM访问命令，将DRAM访问命令存储在DRAM存储体指令FIFO中，并根据DRAM存储体执行优先级设置优先级表。 DRAM命令控制器连接到存储器访问命令并行处理器和用于接收DRAM访问命令的DRAM，并且向DRAM发送控制命令。读取数据缓冲器连接到DRAM命令控制器和用于存储读取数据并重新排列读取数据序列的系统总线。

2. 发明申请

US20110019489A1 Apparatus and method for data strobe and timing variation detection of an SDRAM interface 有权
标题翻译： SDRAM接口的数据选通和定时变化检测的装置和方法
公开(公告)号：US20110019489A1
公开(公告)日：2011-01-27
申请号：US12656216
申请日：2010-01-21
申请人： Ming-Chuan Huang , Chien-Piao Lan , Chia Hao Lee
发明人： Ming-Chuan Huang , Chien-Piao Lan , Chia Hao Lee
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/1051 , G11C7/1093 , G11C8/18
摘要： An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.
摘要翻译：用于SDRAM接口的数据选通和定时变化检测的装置包括差分信号到单端信号转换器，第一相位延迟电路，数据锁存电路。差分信号到单端信号转换器从SDRAM接口接收差分数据选通信号，并将该信号转换为单端数据选通信号。第一相位延迟电路连接到差分信号到单端信号转换器，以延迟单端数据选通信号的相位，以产生延迟的数据选通信号。数据锁存电路连接到相位延迟电路，根据延迟的单端数据选通信号，从SDRAM接口锁存同步数据。

3. 发明授权

US07454574B2 Pre-fetch control method 有权
标题翻译：预取控制方法
公开(公告)号：US07454574B2
公开(公告)日：2008-11-18
申请号：US11327398
申请日：2006-01-09
申请人： Ming Chuan Huang
发明人： Ming Chuan Huang
IPC分类号： G06F12/06 , G06F12/12
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： A pre-fetch control method comprises the following steps. First, after a data request for M-bytes request data sent from a cache controller is received, a determination is made on whether the M-bytes request data are found in the pre-fetch buffer. Then, a further determination is made on whether a combined access control is enabled if the M-bytes request data are not found in the pre-fetch buffer. If the combined access is not enabled, a data request for the M-bytes request data is sent out to an external unit. If the combined access control is enabled, a data request for the M-bytes request data and n*M-bytes extra data is sent out to an external unit. The n*M-bytes extra data is stored in the pre-fetch buffer.
摘要翻译：预取控制方法包括以下步骤。首先，在接收到从高速缓存控制器发送的M字节请求数据的数据请求之后，确定是否在预取缓冲器中找到M字节请求数据。然后，如果在预取缓冲器中没有找到M字节请求数据，则进一步确定是否启用组合访问控制。如果未启用组合访问，则将M字节请求数据的数据请求发送到外部单元。如果组合访问控制被使能，则将M字节请求数据和n * M字节额外数据的数据请求发送到外部单元。 n * M字节额外数据存储在预取缓冲区中。

4. 发明授权

US5203709A Device for coupling a battery to an electric appliance 失效
标题翻译：用于将电池耦合到电器的装置
公开(公告)号：US5203709A
公开(公告)日：1993-04-20
申请号：US884437
申请日：1992-05-18
申请人： Ming-Chuan Huang
发明人： Ming-Chuan Huang
IPC分类号： H01M2/10 , H01M2/20 , H01M6/44 , H01R11/30 , H01R13/62
CPC分类号： H01R13/6205 , H01M2/105 , H01M2/20 , H01M6/44 , H01R11/30
摘要： A device for coupling a battery to an electric appliance including two magnetic plates, one of the magnetic plates having an opening for engagement with a center electrode of the battery, the other magnetic plate attractable to the case electrode of the battery, and a wire for electrically coupling the magnetic plates to the electric appliance in order to energize the electric appliance.
摘要翻译：一种用于将电池耦合到包括两个磁性板的电器的装置，一个磁性板具有用于与电池的中心电极接合的开口，另一个磁性板可吸引到电池的壳体电极，将磁性板电耦合到电器以为电器通电。

5. 发明申请

US20130342805A1 MULTI-FUNCTIONAL EYEGLASSES 审中-公开
标题翻译：多功能眼药水
公开(公告)号：US20130342805A1
公开(公告)日：2013-12-26
申请号：US13528861
申请日：2012-06-21
申请人： Ming Chuan HUANG
发明人： Ming Chuan HUANG
IPC分类号： G02C11/00
CPC分类号： G02C9/02 , G02C11/10
摘要： A multi-functional eyeglasses includes two lenses and an eyeglass frame including two supporting rods and two lens frames; each lens frame being installed with a respective one of the lenses. The multi-functional eyeglasses has a processor, a memory and a display. The eyeglasses can be installed with a receiver and a transmitter, a GPS positioning system, a Bluetooth system, a camera, a sound control system, a TV circuit, a scanner, a clinical thermometer, a thermometer, a batter, a solar energy chip, USP plugs, switching set. This, the functions of eyeglasses are expanded extremely so as to provide great convenience to users.
摘要翻译：多功能眼镜包括两个透镜和一个包括两个支撑杆和两个透镜框架的眼镜框架; 每个透镜框架安装有相应的一个透镜。多功能眼镜具有处理器，存储器和显示器。眼镜可以安装有接收器和发射器，GPS定位系统，蓝牙系统，照相机，声控系统，电视电路，扫描仪，体温计，温度计，面糊，太阳能芯片，USP插头，开关组。这样，眼镜的功能得到极大扩展，为用户提供了极大的方便。

6. 发明申请

US20120239873A1 Memory access system and method for optimizing SDRAM bandwidth 审中-公开
标题翻译：用于优化SDRAM带宽的内存访问系统和方法
公开(公告)号：US20120239873A1
公开(公告)日：2012-09-20
申请号：US13137643
申请日：2011-08-31
申请人： Ming-Chuan Huang , Chia-Hao Lee
发明人： Ming-Chuan Huang , Chia-Hao Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master.
摘要翻译：用于优化SDRAM带宽的存储器访问系统包括存储器命令处理器，以及SDRAM接口和协议控制器。存储器命令处理器连接到存储器总线仲裁器和数据交换电路，用于接收由存储器总线仲裁器和数据开关电路输出的存储器访问命令，并将存储器访问命令转换为重新排序的SDRAM命令。 SDRAM接口和协议控制器连接到存储器命令处理器，用于基于SDRAM的协议和时序接收和执行重新排序的SDRAM命令。存储器命令处理器将存储器访问命令解码为通用SDRAM命令或替代的SDRAM命令。解码为替代SDRAM命令的存储器访问命令由特定总线主机产生。

7. 发明申请

US20100153636A1 CONTROL SYSTEM AND METHOD FOR MEMORY ACCESS 有权
标题翻译：用于存储器访问的控制系统和方法
公开(公告)号：US20100153636A1
公开(公告)日：2010-06-17
申请号：US12635828
申请日：2009-12-11
申请人： Ming Chuan HUANG , Chia Hao Lee , Han Liang Chou
发明人： Ming Chuan HUANG , Chia Hao Lee , Han Liang Chou
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F13/1626
摘要： A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.
摘要翻译：用于存储器访问的控制系统包括系统存储器访问命令缓冲器，存储器访问命令并行处理器，DRAM命令控制器和读取数据缓冲器。系统存储器访问命令缓冲器存储多个系统存储器访问命令。存储器访问命令并行处理器连接到系统存储器访问命令缓冲器，用于将系统存储器访问命令读取和解码为多个DRAM访问命令，将DRAM访问命令存储在DRAM存储体指令FIFO中，并根据DRAM存储体执行优先级设置优先级表。 DRAM命令控制器连接到存储器访问命令并行处理器和用于接收DRAM访问命令的DRAM，并且向DRAM发送控制命令。读取数据缓冲器连接到DRAM命令控制器和用于存储读取数据并重新排列读取数据序列的系统总线。

8. 发明申请

US20050015574A1 Processor and method capable of executing instruction sets with different lengths 审中-公开
标题翻译：能够执行不同长度的指令集的处理器和方法
公开(公告)号：US20050015574A1
公开(公告)日：2005-01-20
申请号：US10742846
申请日：2003-12-23
申请人： Ming-Chuan Huang
发明人： Ming-Chuan Huang
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30076 , G06F9/30149 , G06F9/30189
摘要： A processor and method capable of executing instruction sets with different lengths is disclosed. The instruction sets include at least an N-bit instruction set and a 2N-bit instruction set. The 2N-bit instruction set includes an instruction set switch instruction (ISSI-2N-N). The N-bit instruction set includes an instruction set switch instruction (ISSI-N-2N). When the ISSI-2N-N is fetched, an instruction decoding device and an instruction executing device are switched to an N-bit mode. When the ISSI-N-2N is fetched, the instruction decoding device and the instruction executing device are switched to a 2N-bit mode. In the N-bit mode, the instruction decoding device decodes a fetched 2N bit word as two N-bit instructions and the instruction executing device executes the two decoded N-bit instructions. In the 2N-bit mode, the instruction decoding device decodes a fetched 2N bit word as a 2N-bit instruction and the instruction executing device executes the decoded 2N-bit instruction.
摘要翻译：公开了能够执行不同长度的指令集的处理器和方法。指令集包括至少一个N位指令集和2N位指令集。 2N位指令集包括指令集切换指令（ISSI-2N-N）。 N位指令集包括指令集切换指令（ISSI-N-2N）。当获取ISSI-2N-N时，指令解码装置和指令执行装置被切换到N位模式。当获取ISSI-N-2N时，指令解码装置和指令执行装置被切换到2N位模式。在N位模式中，指令解码装置将取出的2N位字解码为两个N位指令，并且指令执行装置执行两个解码的N位指令。在2N位模式中，指令解码装置将取出的2N位字解码为2N位指令，并且指令执行装置执行解码的2N位指令。

9. 发明授权

US08392768B2 Memory test system with advance features for completed memory system 有权
标题翻译：内存测试系统具有完善的内存系统的先进功能
公开(公告)号：US08392768B2
公开(公告)日：2013-03-05
申请号：US13064513
申请日：2011-03-30
申请人： Chia-Hao Lee , Ming-Chuan Huang
发明人： Chia-Hao Lee , Ming-Chuan Huang
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C11/401
摘要： In a memory test system with advance features for completed memory system, the hardware components are independently configured to generate versatile test patterns for performing a programmable-loading test, a real case test, and a write-feedback test. The write-feedback test is employed to independently test a memory controller which is embedded in an integrated circuit without communicating with the external SDRAM. In the integrated circuit verification stage, the memory test system supports for analyzing and distinguishing the problems inside or outside of the integrated circuit, and testing individual write and read commands.
摘要翻译：在具有完成存储器系统的先进特性的存储器测试系统中，硬件组件被独立地配置为产生用于执行可编程加载测试，实际情况测试和写反馈测试的通用测试模式。写入反馈测试用于独立测试嵌入在集成电路中的存储器控制器，而不与外部SDRAM通信。在集成电路验证阶段，内存测试系统支持分析和区分集成电路内外的问题，并对各个写入和读取命令进行测试。

10. 发明授权

US08208321B2 Apparatus and method for data strobe and timing variation detection of an SDRAM interface 有权
标题翻译： SDRAM接口的数据选通和定时变化检测的装置和方法
公开(公告)号：US08208321B2
公开(公告)日：2012-06-26
申请号：US12656216
申请日：2010-01-21
申请人： Ming-Chuan Huang , Chien-Piao Lan , Chia Hao Lee
发明人： Ming-Chuan Huang , Chien-Piao Lan , Chia Hao Lee
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/1093 , G11C8/18
摘要： An apparatus for data strobe and timing variation detection of an SDRAM interface includes a differential-signal to single-end signal converter, a first phase delay circuit, a data latch circuit. The differential-signal to single-end signal converter receives a differential data strobe signal from the SDRAM interface and converts the signal into a single-end data strobe signal. The first phase delay circuit is connected to the differential-signal to single-end signal converter to delay the phase of the single-end data strobe signal for producing a delayed data strobe signal. The data latch circuit is connected to the phase delay circuit to latch synchronous data from the SDRAM interface according to the delayed single-end data strobe signal.
摘要翻译：用于SDRAM接口的数据选通和定时变化检测的装置包括差分信号到单端信号转换器，第一相位延迟电路，数据锁存电路。差分信号到单端信号转换器从SDRAM接口接收差分数据选通信号，并将该信号转换为单端数据选通信号。第一相位延迟电路连接到差分信号到单端信号转换器，以延迟单端数据选通信号的相位，以产生延迟的数据选通信号。数据锁存电路连接到相位延迟电路，根据延迟的单端数据选通信号，从SDRAM接口锁存同步数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式