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1. 发明申请

US20100169564A1 APPARATUS AND METHOD FOR ACCESSING DATA 审中-公开
标题翻译：用于访问数据的装置和方法
公开(公告)号：US20100169564A1
公开(公告)日：2010-07-01
申请号：US12648305
申请日：2009-12-29
申请人： Han-Liang Chou
发明人： Han-Liang Chou
IPC分类号： G06F12/08
CPC分类号： G06F13/1678
摘要： A data access apparatus and method are provided. The data access apparatus includes a first memory, a second memory and a memory controller. The first memory and the second memory have the same memory capacity for respectively storing the neighbor data of an image. The memory controller is coupled to the first memory and the second memory for providing shared control signals and shared address signals, and further providing a plurality of first address signals and a plurality of second address signals to the first memory and the second memory respectively. The memory controller dynamically accesses the first memory and the second memory by different column address strobe (CAS) signal of the shared control signals, the first address signals and the second address signals.
摘要翻译：提供了数据访问装置和方法。数据存取装置包括第一存储器，第二存储器和存储器控制器。第一存储器和第二存储器具有用于分别存储图像的相邻数据的相同存储器容量。存储器控制器耦合到第一存储器和第二存储器，用于提供共享控制信号和共享地址信号，并且还分别向第一存储器和第二存储器提供多个第一地址信号和多个第二地址信号。存储器控制器通过共享控制信号，第一地址信号和第二地址信号的不同列地址选通（CAS）信号来动态地访问第一存储器和第二存储器。

2. 发明申请

US20100153636A1 CONTROL SYSTEM AND METHOD FOR MEMORY ACCESS 有权
标题翻译：用于存储器访问的控制系统和方法
公开(公告)号：US20100153636A1
公开(公告)日：2010-06-17
申请号：US12635828
申请日：2009-12-11
申请人： Ming Chuan HUANG , Chia Hao Lee , Han Liang Chou
发明人： Ming Chuan HUANG , Chia Hao Lee , Han Liang Chou
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F13/1626
摘要： A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.
摘要翻译：用于存储器访问的控制系统包括系统存储器访问命令缓冲器，存储器访问命令并行处理器，DRAM命令控制器和读取数据缓冲器。系统存储器访问命令缓冲器存储多个系统存储器访问命令。存储器访问命令并行处理器连接到系统存储器访问命令缓冲器，用于将系统存储器访问命令读取和解码为多个DRAM访问命令，将DRAM访问命令存储在DRAM存储体指令FIFO中，并根据DRAM存储体执行优先级设置优先级表。 DRAM命令控制器连接到存储器访问命令并行处理器和用于接收DRAM访问命令的DRAM，并且向DRAM发送控制命令。读取数据缓冲器连接到DRAM命令控制器和用于存储读取数据并重新排列读取数据序列的系统总线。

3. 发明授权

US07720158B2 Memory managing method and video data decoding method 有权
标题翻译：内存管理方法和视频数据解码方法
公开(公告)号：US07720158B2
公开(公告)日：2010-05-18
申请号：US10907562
申请日：2005-04-06
申请人： Ying-Chih Yang , Han-Liang Chou , Jen-Yi Liao
发明人： Ying-Chih Yang , Han-Liang Chou , Jen-Yi Liao
IPC分类号： H04N7/12 , H04N11/02
CPC分类号： H04N19/433 , H04N19/102 , H04N19/159 , H04N19/172 , H04N19/176
摘要： A memory managing method for video data decoding process is provided. The memory managing method includes the following steps. A first frame having a first definition is stored, wherein the first frame is a first type or a second type. A second frame having the first definition is stored, wherein the second frame is the first type or the second type. A first frame having a second definition is stored in the memory space where the first frame having the first definition was originally stored, and the remaining memory space left after the original first frame having the first definition had been stored is released, wherein the memory space for storing the first frame having the first definition is greater than the memory space for storing the first frame having the second definition. A third frame having the second definition is stored, wherein the third frame is a third type.
摘要翻译：提供了一种用于视频数据解码处理的存储器管理方法。存储器管理方法包括以下步骤。存储具有第一定义的第一帧，其中第一帧是第一类型或第二类型。存储具有第一定义的第二帧，其中第二帧是第一类型或第二类型。具有第二定义的第一帧被存储在具有最初存储第一定义的第一帧的存储器空间中，并且剩余的具有第一定义的原始第一帧之后剩余的剩余存储空间被释放，其中存储器空间用于存储具有第一定义的第一帧大于用于存储具有第二定义的第一帧的存储器空间。存储具有第二定义的第三帧，其中第三帧是第三类型。

4. 发明申请

US20060083313A1 MEMORY MANAGING METHOD AND VIDEO DATA DECODING METHOD 有权
标题翻译：存储器管理方法和视频数据解码方法
公开(公告)号：US20060083313A1
公开(公告)日：2006-04-20
申请号：US10907562
申请日：2005-04-06
申请人： Ying-Chih Yang , Han-Liang Chou , Jen-Yi Liao
发明人： Ying-Chih Yang , Han-Liang Chou , Jen-Yi Liao
IPC分类号： H04N11/02 , H04N7/12 , H04N11/04 , H04B1/66
CPC分类号： H04N19/433 , H04N19/102 , H04N19/159 , H04N19/172 , H04N19/176
摘要： A memory managing method for video data decoding process is provided. The memory managing method includes the following steps. A first frame having a first definition is stored, wherein the first frame is a first type or a second type. A second frame having the first definition is stored, wherein the second frame is the first type or the second type. A first frame having a second definition is stored in the memory space where the first frame having the first definition was originally stored, and the remaining memory space left after the original first frame having the first definition had been stored is released, wherein the memory space for storing the first frame having the first definition is greater than the memory space for storing the first frame having the second definition. A third frame having the second definition is stored, wherein the third frame is a third type.
摘要翻译：提供了一种用于视频数据解码处理的存储器管理方法。存储器管理方法包括以下步骤。存储具有第一定义的第一帧，其中第一帧是第一类型或第二类型。存储具有第一定义的第二帧，其中第二帧是第一类型或第二类型。具有第二定义的第一帧被存储在具有最初存储第一定义的第一帧的存储器空间中，并且剩余的具有第一定义的原始第一帧之后剩余的剩余存储空间被释放，其中存储器空间用于存储具有第一定义的第一帧大于用于存储具有第二定义的第一帧的存储器空间。存储具有第二定义的第三帧，其中第三帧是第三类型。

5. 发明授权

US07688896B2 Method and apparatus for decoding compressed video image data 有权
标题翻译：压缩视频图像数据解码方法和装置
公开(公告)号：US07688896B2
公开(公告)日：2010-03-30
申请号：US11045097
申请日：2005-01-31
申请人： Ying-Chih Yang , Han-Liang Chou , Jen-Yi Liao
发明人： Ying-Chih Yang , Han-Liang Chou , Jen-Yi Liao
IPC分类号： H04N7/12 , H04N7/137
CPC分类号： H04N19/427
摘要： A method and an apparatus for decoding video image data including a plurality of frames are provided. Each of the frames includes a reserved portion and a non-reserved portion. The method comprises decoding only the non-reserved portion of one of the frames and displaying the decoded non-reserved portion of the frame and the reserved portion of a previously decoded frame. The apparatus comprises a decoding device to decode the non-reserved portion of one of the frames and a displaying device to display the reserved portion of a previously decoded frame and the decoded non-reserved portion of the frame.
摘要翻译：提供了一种用于解码包括多个帧的视频图像数据的方法和装置。每个帧包括保留部分和非保留部分。该方法包括仅对帧中的一个的非保留部分进行解码，并且显示帧的解码非保留部分和先前解码的帧的保留部分。该装置包括：解码装置，用于对帧中的一个的非保留部分进行解码;以及显示装置，用于显示先前解码的帧的预留部分和帧的经解码的非保留部分。

6. 发明授权

US07296102B2 Method and chip to expand pins of the chip 失效
标题翻译：方法和芯片来扩展芯片的引脚
公开(公告)号：US07296102B2
公开(公告)日：2007-11-13
申请号：US10710766
申请日：2004-08-02
申请人： Yu-Cheng Nieh , Han-Liang Chou
发明人： Yu-Cheng Nieh , Han-Liang Chou
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/385
摘要： A method and a chip for expanding pins of a chip are disclosed. A first interface of a first chip transmits an encoded second interface command. When a second chip receives the encoded second command, a second chip decodes the encoded second interface command and transmits allowing the pins of the second chip to transmit the second interface command and thereby achieve the expansion of pins of the first chip. Because of the low pin count of the second chip that can accommodate pins of the first chip, there is no need to increase the pin count of the first chip, therefore the packaging cost of the first chip is substantially reduced without significantly increasing the packaging cost for the second chip.
摘要翻译：公开了一种用于扩展芯片引脚的方法和芯片。第一芯片的第一接口发送编码的第二接口命令。当第二芯片接收到编码的第二命令时，第二芯片解码编码的第二接口命令，并发送允许第二芯片的引脚发送第二接口命令，从而实现第一芯片的引脚的扩展。由于可以容纳第一芯片的引脚的第二芯片的引脚数量低，因此不需要增加第一芯片的引脚数，因此第一芯片的封装成本显着降低，而不显着增加封装成本对于第二个芯片

7. 发明申请

US20060236204A1 MEMORY DEVICE WITH SERIAL TRANSMISSION INTERFACE AND ERROR CORRECTION MEHTOD FOR SERIAL TRANSMISSION INTERFACE 审中-公开
标题翻译：具有串行传输接口和错误校正装置的串行传输接口的存储器件
公开(公告)号：US20060236204A1
公开(公告)日：2006-10-19
申请号：US11161957
申请日：2005-08-24
申请人： Yu-Chu Lee , Shih-Yu Huang , Han-Liang Chou
发明人： Yu-Chu Lee , Shih-Yu Huang , Han-Liang Chou
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1068 , G11C7/1051 , G11C7/1078 , G11C2207/104 , G11C2207/107
摘要： The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial transmission interface accesses the memory. Further, the action of error corrections and data re-transmissions performed by the master device can be reduced.
摘要翻译：本发明提供一种具有串行传输接口和用于串行传输接口的纠错方法的存储器件。存储装置包括错误校正机构，用于早期检测或自动校正错误，以确保在串行传输接口访问存储器时数据传输的正确性。此外，可以减少由主设备执行的错误校正和数据重传的动作。

8. 发明申请

US20050256982A1 [METHOD AND CHIP TO EXPAND PINS OF THE CHIP] 失效
标题翻译： [插入芯片的方法和芯片]
公开(公告)号：US20050256982A1
公开(公告)日：2005-11-17
申请号：US10710766
申请日：2004-08-02
申请人： Yu-Cheng Nieh , Han-Liang Chou
发明人： Yu-Cheng Nieh , Han-Liang Chou
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/385
摘要： A method and a chip for expanding pins of a chip are disclosed. A first interface of a first chip transmits an encoded second interface command. When a second chip receives the encoded second command, a second chip decodes the encoded second interface command and transmits allowing the pins of the second chip to transmit the second interface command and thereby achieve the expansion of pins of the first chip. Because of the low pin count of the second chip that can accommodate pins of the first chip, there is no need to increase the pin count of the first chip, therefore the packaging cost of the first chip is substantially reduced without significantly increasing the packaging cost for the second chip.
摘要翻译：公开了一种用于扩展芯片引脚的方法和芯片。第一芯片的第一接口发送编码的第二接口命令。当第二芯片接收到编码的第二命令时，第二芯片解码编码的第二接口命令，并发送允许第二芯片的引脚发送第二接口命令，从而实现第一芯片的引脚的扩展。由于可以容纳第一芯片的引脚的第二芯片的引脚数量低，因此不需要增加第一芯片的引脚数，因此第一芯片的封装成本显着降低，而不显着增加封装成本对于第二个芯片

9. 发明授权

US06931157B2 Bi-directional motion compensation method to reduce the number of registers 失效
标题翻译：双向运动补偿方法减少寄存器数量
公开(公告)号：US06931157B2
公开(公告)日：2005-08-16
申请号：US10844951
申请日：2004-05-12
申请人： Ying-Chih Yang , Han-Liang Chou
发明人： Ying-Chih Yang , Han-Liang Chou
IPC分类号： G06K9/36 , H04N7/12 , H04N7/26
CPC分类号： H04N19/43
摘要： A method for bi-directional motion compensation is provided. The method comprises: adding the predicted error twice, the first predictor, and one to obtain a first calculation result; wherein if the first calculation result is larger than a maximum positive value storable in the register, either the maximum positive value or a value of the maximum positive value minus one is stored in the register, otherwise the first calculation result is stored in the register; adding the value stored in the register and the second predictor to obtain a second calculation result; wherein if the second calculation result is larger than the maximum positive value storable in the register, either the maximum positive value or the value of the maximum positive value minus one is stored in the register, if the second calculation result is smaller than zero, a zero is stored in the register, otherwise the second calculation result is stored in the register; right-shifting the value one bit to obtain the pixel data.
摘要翻译：提供了一种用于双向运动补偿的方法。所述方法包括：将所述预测误差加上所述第一预测器，并且获得第一计算结果; 其中如果第一计算结果大于可存储在寄存器中的最大正值，则将最大正值或最大正值减去1的值存储在寄存器中，否则将第一计算结果存储在寄存器中; 将存储在寄存器和第二预测器中的值相加以获得第二计算结果; 其中如果第二计算结果大于可存储在寄存器中的最大正值，则如果第二计算结果小于零，则最大正值或最大正值减1的值被存储在寄存器中，a 零存储在寄存器中，否则第二个计算结果存储在寄存器中; 将值右移一位以获得像素数据。

10. 发明授权

US08250322B2 Command reordering based on command priority 有权
标题翻译：基于命令优先级的命令重新排序
公开(公告)号：US08250322B2
公开(公告)日：2012-08-21
申请号：US12635828
申请日：2009-12-11
申请人： Ming Chuan Huang , Chia Hao Lee , Han Liang Chou
发明人： Ming Chuan Huang , Chia Hao Lee , Han Liang Chou
IPC分类号： G06F13/18
CPC分类号： G06F12/0607 , G06F13/1626
摘要： A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.
摘要翻译：用于存储器访问的控制系统包括系统存储器访问命令缓冲器，存储器访问命令并行处理器，DRAM命令控制器和读取数据缓冲器。系统存储器访问命令缓冲器存储多个系统存储器访问命令。存储器访问命令并行处理器连接到系统存储器访问命令缓冲器，用于将系统存储器访问命令读取和解码为多个DRAM访问命令，将DRAM访问命令存储在DRAM存储体指令FIFO中，并根据DRAM存储体执行优先级设置优先级表。 DRAM命令控制器连接到存储器访问命令并行处理器和用于接收DRAM访问命令的DRAM，并且向DRAM发送控制命令。读取数据缓冲器连接到DRAM命令控制器和用于存储读取数据并重新排列读取数据序列的系统总线。

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