专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07717060B2 Controlled electroless plating 有权
标题翻译：受控化学镀
公开(公告)号：US07717060B2
公开(公告)日：2010-05-18
申请号：US11610768
申请日：2006-12-14
申请人： Steven M. Hues , Michael L. Lovejoy , Varughese Mathew
发明人： Steven M. Hues , Michael L. Lovejoy , Varughese Mathew
IPC分类号： B05C11/00
CPC分类号： H01L21/288 , C23C18/1617 , C23C18/50 , C23C18/52 , H01L21/76849
摘要： An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.
摘要翻译：制造半导体器件的无电金属沉积工艺使用具有还原剂的镀浴溶液。取出溶液的样品，并增加样品的pH。测量从样品放出的氢。放出的氢被用于测定样品中存在的还原剂的浓度。基于确定的还原剂浓度，对镀液溶液进行改性。

2. 发明授权

US06789220B1 Method and apparatus for vector processing 有权
标题翻译：用于矢量处理的方法和装置
公开(公告)号：US06789220B1
公开(公告)日：2004-09-07
申请号：US09849859
申请日：2001-05-03
申请人： Michael L. Lovejoy
发明人： Michael L. Lovejoy
IPC分类号： G01R313177
CPC分类号： G01R31/31921
摘要： A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift register is used to perform a first vector space reduction, and the MISR is used to perform a second vector space compression. Accordingly the MISR may be scaled down in input width by a reduction factor of the shift register.
摘要翻译：描述了用于测试矢量压缩的方法和装置。更具体地，描述了具有移位寄存器和多输入签名寄存器的响应分析器。移位寄存器用于执行第一向量空间缩减，MISR用于执行第二向量空间压缩。因此，MISR可以通过移位寄存器的缩小因子在输入宽度上缩小。

3. 发明授权

US07436726B1 Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data 有权
标题翻译：包括用于重新读取数据的备份地址电路的异步FIFO中数据读取的电路和方法
公开(公告)号：US07436726B1
公开(公告)日：2008-10-14
申请号：US11285125
申请日：2005-11-21
申请人： Michael L. Lovejoy
发明人： Michael L. Lovejoy
IPC分类号： G11C7/00
CPC分类号： G06F5/10 , G06F2205/062 , H04L49/90
摘要： A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write address count, while a read address counter stores a read address count. Finally, a backup circuit receives a read address associated with data read from a slot of the plurality of slots. According to an alternate embodiment, a most significant bit circuit is coupled to an output of the write address counter for setting the most significant bit of the write address. A method of reading data stored in an asynchronous FIFO memory of an integrated circuit is also disclosed.
摘要翻译：描述了一种用于在集成电路的异步FIFO存储器中读取数据的电路。该电路包括存储多个具有相应多个地址的时隙中的数据的存储器。写入地址计数器存储写入地址计数，而读取地址计数器存储读取地址计数。最后，备用电路接收与从多个时隙中的时隙读取的数据相关联的读地址。根据替代实施例，最高有效位电路耦合到写入地址计数器的输出端，用于设置写入地址的最高有效位。还公开了一种读取存储在集成电路的异步FIFO存储器中的数据的方法。

4. 发明授权

US07052962B1 Non-volatile memory cell and method of manufacturing a non-volatile memory cell 失效
标题翻译：非易失性存储单元以及制造非易失性存储单元的方法
公开(公告)号：US07052962B1
公开(公告)日：2006-05-30
申请号：US10959388
申请日：2004-10-06
申请人： Michael L. Lovejoy
发明人： Michael L. Lovejoy
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.
摘要翻译：公开了集成在集成电路中的非易失性存储单元。非易失性存储单元包括存取晶体管; 耦合到所述存取晶体管的浮栅晶体管; 形成在所述存取晶体管的源极和所述第二晶体管的栅极之间的隧穿电容器; 以及耦合电容器，其具有与所述浮栅晶体管的栅极相关联的第一板，所述第一板被形成为使所述浮栅晶体管的栅极 - 源极电容最小化。还创建了一个窗口来减小隧道电容器的电容和浮栅晶体管的栅极到源极电容。还公开了制造该非易失性存储单元的方法。

5. 发明授权

US6031454A Worker-specific exposure monitor and method for surveillance of workers 失效
标题翻译：工人专用暴露监测和工作监督方法
公开(公告)号：US6031454A
公开(公告)日：2000-02-29
申请号：US969258
申请日：1997-11-13
申请人： Michael L. Lovejoy , John P. Peeters , A. Wayne Johnson
发明人： Michael L. Lovejoy , John P. Peeters , A. Wayne Johnson
IPC分类号： G01T1/02 , G01T7/00 , G08B1/08 , G08B23/00
CPC分类号： G01T1/026 , G01N33/0075 , G01T7/00
摘要： A person-specific monitor that provides sensor information regarding hazards to which the person is exposed and means to geolocate the person at the time of the exposure. The monitor also includes means to communicate with a remote base station. Information from the monitor can be downloaded at the base station for long term storage and analysis. The base station can also include means to recharge the monitor.
摘要翻译：提供有关人员暴露的危害的传感器信息的人员监视器，以及在暴露时对人员进行地理定位的手段。监视器还包括与远程基站进行通信的手段。来自监控器的信息可以在基站下载，以进行长期存储和分析。基站还可以包括为显示器充电的方法。

6. 发明授权

US07527976B2 Processes for testing a region for an analyte and a process for forming an electronic device 有权
标题翻译：用于测试分析物的区域和用于形成电子设备的过程的方法
公开(公告)号：US07527976B2
公开(公告)日：2009-05-05
申请号：US11060833
申请日：2005-02-18
申请人： Steven M. Hues , Hassan F. Fakhreddine , Michael L. Lovejoy , David D. Sieloff
发明人： Steven M. Hues , Hassan F. Fakhreddine , Michael L. Lovejoy , David D. Sieloff
IPC分类号： G01N21/62
CPC分类号： G01N23/223 , G01N2223/076
摘要： A workpiece, including a substrate and overlying layer, can be exposed to a region, such as a process chamber, to test for the presence of an analyte. Detected fluorescence emission signals during TXRD due to the substrate are significantly reduced, allowing the analyte to be detected at lower concentrations. In one embodiment, the substrate can principally include silicon, and the layer can include an organic layer (e.g., resist, polyimide, etc.) The organic layer allows analytes with an atomic number as low as 11 to be detected. Also, the detection limits for nearly all analytes can be reduced because the detector is not receiving a disproportionately larger number of fluorescence emission from silicon. In additional, areal information regarding the analyte with respect to position over the substrate can be obtained. Detection levels as low as 1E9 atoms/cm2 are possible.
摘要翻译：包括衬底和上覆层的工件可以暴露于诸如处理室的区域以测试分析物的存在。由于底物而在TXRD期间检测到的荧光发射信号显着降低，从而以更低的浓度检测分析物。在一个实施例中，衬底可以主要包括硅，并且该层可以包括有机层（例如，抗蚀剂，聚酰亚胺等）。有机层允许检测到原子序数低至11的分析物。此外，几乎所有分析物的检测限可以减少，因为检测器没有从硅中获得不成比例的较大数量的荧光发射。另外，可以获得关于分析物相对于衬底上的位置的面积信息。低至1E9原子/ cm2的检测水平是可能的。

7. 发明授权

US06822254B1 Non-volatile memory cell 有权
标题翻译：非易失性存储单元
公开(公告)号：US06822254B1
公开(公告)日：2004-11-23
申请号：US10407516
申请日：2003-04-04
申请人： Michael L. Lovejoy
发明人： Michael L. Lovejoy
IPC分类号： H01L2906
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.
摘要翻译：公开了集成在集成电路中的非易失性存储单元。非易失性存储单元包括存取晶体管; 耦合到所述存取晶体管的浮栅晶体管; 形成在所述存取晶体管的源极和所述第二晶体管的栅极之间的隧穿电容器; 以及耦合电容器，其具有与所述浮栅晶体管的栅极相关联的第一板，所述第一板被形成为使所述浮栅晶体管的栅极 - 源极电容最小化。还创建了一个窗口来减小隧道电容器的电容和浮栅晶体管的栅极到源极电容。还公开了制造该非易失性存储单元的方法。

8. 发明授权

US06437605B1 Dynamic sense amplifier for low-power applications 有权
标题翻译：用于低功耗应用的动态读出放大器
公开(公告)号：US06437605B1
公开(公告)日：2002-08-20
申请号：US09767273
申请日：2001-01-22
申请人： Michael L. Lovejoy
发明人： Michael L. Lovejoy
IPC分类号： G11C706
CPC分类号： G11C7/067
摘要： A sense amplifier (10) is disclosed comprising: a connecting node (12) connectable to a plurality of logic cells (13) for reading the logic states thereof; at least one output (16, 18, 20); circuitry (14) for transferring the read logic states from the connecting node (12) to the at least one output; and a circuit (50) dynamically operative to limit the voltage at the connecting node (12) substantially to a predetermined voltage. In one embodiment, the circuit (50) includes a pass transistor (46) coupled between the connecting node (12) and the transferring circuit (14) and operative to conduct the logic states read from the logic cells to the transferring circuit; and a capacitive divider circuit (54, 56) coupled to a voltage source (Vdd) for producing at a node (52) thereof the predetermined voltage as a fraction of the voltage of the source, the node (52) being coupled to the pass transistor (46) to limit the voltage at the connecting node (12) substantially to the predetermined voltage. In another embodiment, the capacitive divider circuit is dynamically operative in accordance with a duty cycle.
摘要翻译：公开了一种读出放大器（10），包括：可连接到多个逻辑单元（13）的连接节点（12），用于读取其逻辑状态; 至少一个输出（16,18,20）; 用于将读逻辑状态从连接节点（12）传送到至少一个输出的电路（14）; 以及动态地操作以将连接节点（12）处的电压基本上限制到预定电压的电路（50）。在一个实施例中，电路（50）包括耦合在连接节点（12）和传输电路（14）之间的传输晶体管（46），并且可操作以将从逻辑单元读取的逻辑状态传导到传送电路; 以及耦合到电压源（Vdd）的电容分压器电路（Vdd），用于在其节点（52）处产生预定电压作为源的电压的一部分，所述节点（52）耦合到通过晶体管（46），以将连接节点（12）处的电压基本上限制到预定电压。在另一个实施例中，电容分压器电路根据占空比动态地工作。

9. 发明授权

US07176133B2 Controlled electroless plating 有权
标题翻译：受控化学镀
公开(公告)号：US07176133B2
公开(公告)日：2007-02-13
申请号：US10994720
申请日：2004-11-22
申请人： Steven M. Hues , Michael L. Lovejoy , Varughese Mathew
发明人： Steven M. Hues , Michael L. Lovejoy , Varughese Mathew
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , C23C18/1617 , C23C18/50 , C23C18/52 , H01L21/76849
摘要： An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.
摘要翻译：制造半导体器件的无电金属沉积工艺使用具有还原剂的镀浴溶液。取出溶液的样品，并增加样品的pH。测量从样品放出的氢。放出的氢被用于测定样品中存在的还原剂的浓度。基于确定的还原剂浓度，对镀液溶液进行改性。

10. 发明授权

US5684308A CMOS-compatible InP/InGaAs digital photoreceiver 失效
标题翻译： CMOS兼容InP / InGaAs数字光电接收器
公开(公告)号：US5684308A
公开(公告)日：1997-11-04
申请号：US601904
申请日：1996-02-15
申请人： Michael L. Lovejoy , Benny H. Rose , David C. Craft , Paul M. Enquist , David B. Slater, Jr.
发明人： Michael L. Lovejoy , Benny H. Rose , David C. Craft , Paul M. Enquist , David B. Slater, Jr.
IPC分类号： H01L27/144 , H01L31/0232
CPC分类号： H01L27/1443
摘要： A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.
摘要翻译：数字光接收器在InP半导体衬底上单片形成，并且包括由通过外延生长工艺沉积的多个InP / InGaAs层和由相同InP / InGaAs层形成的相邻异质结双极晶体管（HBT）放大器形成的p-i-n光电检测器。光接收放大器工作在大信号模式，以将检测到的光电流信号转换成能够直接驱动诸如CMOS的集成电路的放大输出。结合光发射机，光接收器可用于建立集成电路与多芯片模块（MCM）应用之间的数字光通信的短距离通道。光接收器还可以与光纤耦合一起使用，用于在分布式计算机之间建立较长范围的数字通信（即光学互连）等。数字光接收器的阵列可以形成在公共衬底上，用于建立多个数字光通信通道，每个光接收器间隔小于约1mm，消耗小于约20mW的功率，优选小于约10mW 。这样的光接收器阵列可用于以高达约1000Mb / s或更高的比特率在集成电路之间传送大量的数字数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式