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1. 发明授权

US07095061B2 Contacting scheme for large and small area semiconductor light emitting flip chip devices 有权
标题翻译：大面积和小面积半导体发光倒装芯片器件的接触方案
公开(公告)号：US07095061B2
公开(公告)日：2006-08-22
申请号：US10961239
申请日：2004-10-07
申请人： Daniel A. Steigerwald , Jerome C. Bhat , Michael J. Ludowise
发明人： Daniel A. Steigerwald , Jerome C. Bhat , Michael J. Ludowise
IPC分类号： H01L33/00
CPC分类号： H01L33/382 , H01L33/08 , H01L33/20 , H01L33/486 , H01L2224/48247
摘要： A light emitting device includes a layer of first conductivity type, a layer of second conductivity type, and a light emitting layer disposed between the layer of first conductivity type and the layer of second conductivity type. A via is formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, diffusion, or selective growth of at least one layer of second conductivity type. A first contact electrically contacts the layer of first conductivity type through the via. A second contact electrically contacts the layer of second conductivity type. A ring that surrounds the light emitting layer and is electrically connected to the first contact electrically contacts the layer of first conductivity type.
摘要翻译：发光器件包括第一导电类型的层，第二导电类型的层和设置在第一导电类型层和第二导电类型层之间的发光层。通孔形成在第二导电类型的层中，直到第一导电类型的层。通孔可以通过例如至少一层第二导电类型的蚀刻，离子注入，扩散或选择性生长来形成。第一接触件通过通孔电接触第一导电类型的层。第二接触件电接触第二导电类型的层。围绕发光层并与第一接触电连接的环电接触第一导电类型的层。

2. 发明授权

US06429466B2 Integrated circuit substrate that accommodates lattice mismatch stress 有权
标题翻译：集成电路基板，适应晶格失配应力
公开(公告)号：US06429466B2
公开(公告)日：2002-08-06
申请号：US09774199
申请日：2001-01-29
申请人： Yong Chen , Scott W. Corzine , Theodore I. Kamins , Michael J. Ludowise , Pierre H. Mertz , Shih-Yuan Wang
发明人： Yong Chen , Scott W. Corzine , Theodore I. Kamins , Michael J. Ludowise , Pierre H. Mertz , Shih-Yuan Wang
IPC分类号： H01L31072
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02538 , H01L21/0254 , H01L21/02658 , H01L21/26533
摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.
摘要翻译：一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。然后将第二种材料在生长温度下沉积在生长表面上。衬底的隔离层的厚度小于在其上结晶第二材料时在第一材料的晶格中产生缺陷的厚度。掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。本发明可用于在硅衬底上生长III-V半导体材料层。在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

3. 发明授权

US06946685B1 Light emitting semiconductor method and device 有权
标题翻译：发光半导体方法及器件
公开(公告)号：US06946685B1
公开(公告)日：2005-09-20
申请号：US09652194
申请日：2000-08-31
申请人： Daniel A. Steigerwald , Michael J. Ludowise , Steven A. Maranowski , Serge L. Rudaz , Jerome C. Bhat
发明人： Daniel A. Steigerwald , Michael J. Ludowise , Steven A. Maranowski , Serge L. Rudaz , Jerome C. Bhat
IPC分类号： H01L29/22 , H01L33/32 , H01L33/40
CPC分类号： H01L33/405 , H01L33/32
摘要： Silver electrode metallization in light emitting devices is subject to electrochemical migration in the presence of moisture and an electric field. Electrochemical migration of the silver metallization to the pn junction of the device results in an alternate shunt path across the junction, which degrades efficiency of the device. In accordance with a form of this invention, a migration barrier is provided for preventing migration of metal from at least one of the electrodes onto the surface of the semiconductor layer with which the electrode is in contact.
摘要翻译：发光器件中的银电极金属化在水分和电场的存在下经历电化学迁移。银金属化物到器件的pn结的电化学迁移导致跨接头的交替分流路径，这降低了器件的效率。根据本发明的形式，提供了一种迁移屏障，用于防止金属从至少一个电极移动到与电极接触的半导体层的表面上。

4. 发明授权

US06946309B2 III-Phosphide and III-Arsenide flip chip light-emitting devices 有权
标题翻译： III型磷化物和III型砷化物倒装芯片发光器件
公开(公告)号：US06946309B2
公开(公告)日：2005-09-20
申请号：US10867936
申请日：2004-06-14
申请人： Michael D. Camras , Daniel A. Steigerwald , Frank M. Steranka , Michael J. Ludowise , Paul S. Martin , Michael R. Krames , Fred A. Kish , Stephen A. Stockman
发明人： Michael D. Camras , Daniel A. Steigerwald , Frank M. Steranka , Michael J. Ludowise , Paul S. Martin , Michael R. Krames , Fred A. Kish , Stephen A. Stockman
IPC分类号： H01L33/02 , H01L33/08 , H01L33/14 , H01L33/20 , H01L21/00
CPC分类号： H01L33/20 , H01L33/02 , H01L33/08 , H01L33/14 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/05611 , H01L2924/00014 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684
摘要： A light-emitting semiconductor device includes a stack of layers including an active region. The active region includes a semiconductor selected from the group consisting of III-Phosphides, III-Arsenides, and alloys thereof. A superstrate substantially transparent to light emitted by the active region is disposed on a first side of the stack. First and second electrical contacts electrically coupled to apply a voltage across the active region are disposed on a second side of the stack opposite to the first side. In some embodiments, a larger fraction of light emitted by the active region exits the stack through the first side than through the second side. Consequently, the light-emitting semiconductor device may be advantageously mounted as a flip chip to a submount, for example.
摘要翻译：发光半导体器件包括包括有源区的层叠层。有源区包括选自III-磷化物，III-砷化物及其合金的半导体。对于由有源区域发射的光基本透明的覆盖层设置在堆叠的第一侧上。电耦合以在有源区域施加电压的第一和第二电触点设置在与第一侧相对的堆叠的第二侧上。在一些实施例中，由有源区域发射的较大部分的光通过第一侧离开堆叠而不是通过第二侧。因此，例如，发光半导体器件可以有利地作为倒装芯片安装到基座。

5. 发明授权

US06828596B2 Contacting scheme for large and small area semiconductor light emitting flip chip devices 有权
标题翻译：大面积和小面积半导体发光倒装芯片器件的接触方案
公开(公告)号：US06828596B2
公开(公告)日：2004-12-07
申请号：US10172311
申请日：2002-06-13
申请人： Daniel A. Steigerwald , Jerome C. Bhat , Michael J. Ludowise
发明人： Daniel A. Steigerwald , Jerome C. Bhat , Michael J. Ludowise
IPC分类号： H01L3300
CPC分类号： H01L33/382 , H01L33/08 , H01L33/20 , H01L33/486 , H01L2224/48247
摘要： In accordance with the invention, a light emitting device includes a substrate, a layer of first conductivity type overlying the substrate, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A plurality of vias are formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, or selective growth of the layer of second conductivity type. A set of first contacts electrically contacts the layer of first conductivity type through the vias. A second contact electrically contacts the layer of second conductivity type. In some embodiments, the area of the second contact is at least 75% of the area of the device. In some embodiments, the vias are between 2 and 100 microns wide and spaced between 5 and 1000 microns apart.
摘要翻译：根据本发明，发光器件包括衬底，覆盖衬底的第一导电类型的层，覆盖第一导电类型的层的发光层和覆盖发光层的第二导电类型的层。在第二导电类型的层中形成多个通孔，直到第一导电类型的层。通孔可以通过例如第二导电类型的蚀刻，离子注入或选择性生长来形成。一组第一触点通过通孔与第一导电类型的层电接触。第二接触件电接触第二导电类型的层。在一些实施例中，第二触点的面积为器件面积的至少75％。在一些实施例中，通孔的宽度为2至100微米，间隔5至1000微米。

6. 发明授权

US06211095B1 Method for relieving lattice mismatch stress in semiconductor devices 有权
标题翻译：减少半导体器件晶格失配应力的方法
公开(公告)号：US06211095B1
公开(公告)日：2001-04-03
申请号：US09221025
申请日：1998-12-23
申请人： Yong Chen , Scott W. Corzine , Theodore I. Kamins , Michael J. Ludowise , Pierre H. Mertz , Shih-Yuan Wang
发明人： Yong Chen , Scott W. Corzine , Theodore I. Kamins , Michael J. Ludowise , Pierre H. Mertz , Shih-Yuan Wang
IPC分类号： H01L2131
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02538 , H01L21/0254 , H01L21/02658 , H01L21/26533
摘要： A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The first material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the second material by the first material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates. In the case of silicon-based substrates, the buried layer is preferably SiO2 that is sufficiently malleable at the growth temperature to allow the deformation of the isolated substrate layer.
摘要翻译：一种用于生长晶体层的方法，其包括在第二材料的晶体衬底的生长表面上的第一材料，其中第一材料和第二材料具有不同的晶格常数。在衬底中产生掩埋层，使得掩埋层将衬底的包含生长表面的衬底与衬底的其余部分隔离。然后在生长温度下将第一种材料沉积在生长表面上。衬底的隔离层的厚度小于通过第一材料在其上结晶而在第二材料的晶格中引起缺陷的厚度。掩埋层在生长温度下具有足够的延展性，以允许隔离层的晶格变形，而不使基底的其余部分变形。本发明可用于在硅衬底上生长III-V半导体材料层。在硅基基板的情况下，掩埋层优选是在生长温度下足够有韧性的SiO 2，以允许隔离的基底层的变形。

7. 发明申请

US20090159122A1 Leadframe Receiver Package 审中-公开
标题翻译：引线框接收器封装
公开(公告)号：US20090159122A1
公开(公告)日：2009-06-25
申请号：US12250034
申请日：2008-10-13
申请人： Gill Shook , Hing Wah Chan , Michael J. Ludowise
发明人： Gill Shook , Hing Wah Chan , Michael J. Ludowise
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L31/048 , Y02E10/50
摘要： The invention is a leadframe receiver package comprising a first conductive element, a solar cell electrically coupled to the first conductive element and comprising an active area, and a mold compound disposed on the leadframe and the solar cell. The mold compound defines a first aperture wall over at least a portion of the active area and a second aperture wall over at least a portion of the first conductive element. The mold compound includes a reflective surface to improve heat resistance around an aperture wall receiving solar radiation.
摘要翻译：本发明是一种引线框接收器封装，包括第一导电元件，电耦合到第一导电元件并且包括有源区的太阳能电池，以及设置在引线框架和太阳能电池上的模具化合物。模具化合物限定有效区域的至少一部分上的第一孔壁和位于第一导电元件的至少一部分上的第二孔壁。模具化合物包括反射表面，以改善围绕接收太阳辐射的孔壁的耐热性。

8. 发明授权

US06995402B2 Integrated reflector cup for a light emitting device mount 有权
标题翻译：用于发光装置安装的集成反射杯
公开(公告)号：US06995402B2
公开(公告)日：2006-02-07
申请号：US10678279
申请日：2003-10-03
申请人： Michael J. Ludowise , Jerome C. Bhat
发明人： Michael J. Ludowise , Jerome C. Bhat
IPC分类号： H01L29/22 , H01L29/205 , H01L29/207
CPC分类号： H01L33/60 , H01L33/62 , H01L2224/16
摘要： A mount for a semiconductor light emitting device includes an integrated reflector cup. The reflector cup includes a wall formed on the mount and shaped and positioned to reflect side light emitted from the light emitting device along a vertical axis of the device/mount combination. The wall may be covered by a reflective material such as a reflective metal.
摘要翻译：用于半导体发光器件的安装件包括集成的反射杯。反射杯包括形成在安装件上的壁，其形状和定位成沿着装置/安装组合的垂直轴反射从发光装置发射的侧光。壁可以被诸如反射金属的反射材料覆盖。

9. 发明申请

US20100263713A1 Four Terminal Monolithic Multijunction Solar Cell 审中-公开
标题翻译：四端子单片多功能太阳能电池
公开(公告)号：US20100263713A1
公开(公告)日：2010-10-21
申请号：US12573142
申请日：2009-10-04
申请人： Michael J. Ludowise
发明人： Michael J. Ludowise
IPC分类号： H01L31/042 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/02021 , H01L31/0687 , H01L31/0725 , Y02E10/544
摘要： A monolithic multijunction photovoltaic device is disclosed which comprises two or more photovoltaic cells between two surfaces. Each of the photovoltaic cell materials include a first region exhibiting an excess of a first charge carrier and a second region exhibiting an excess of a second charge carrier. Contacts are connected to the regions of the photovoltaic cells in configurations that allow excess current to be extracted as useful energy. In one embodiment, a first contact is electrically connected to a second region of a first material, a second contact is electrically connected to a first region of the first material, a third contact is electrically connected to a first region of a second material, and a fourth contact is electrically connected to a third material. In other embodiments, the contacts may be positioned on the surfaces of the monolithic device to minimize shadowing.
摘要翻译：公开了一种在两个表面之间包括两个或多个光伏电池的单片多结光伏器件。每个光伏电池材料包括表现出过量的第一电荷载流子的第一区域和表现出过量的第二电荷载流子的第二区域。接触件以允许作为有用能量提取过量电流的结构连接到光伏电池的区域。在一个实施例中，第一触点电连接到第一材料的第二区域，第二触点电连接到第一材料的第一区域，第三触点电连接到第二材料的第一区域，以及第四触点电连接到第三材料。在其它实施例中，触点可以定位在单片设备的表面上以最小化阴影。

10. 发明申请

US20090277503A1 Solar Cell with Current Blocking Layer 审中-公开
标题翻译：具有电流阻挡层的太阳能电池
公开(公告)号：US20090277503A1
公开(公告)日：2009-11-12
申请号：US12401546
申请日：2009-03-10
申请人： Michael J. Ludowise
发明人： Michael J. Ludowise
IPC分类号： H01L31/00 , B05D7/00
CPC分类号： H01L31/022433 , H01L31/054 , Y02E10/50
摘要： A solar cell includes an active layer, a blocking layer and a contact layer. The blocking layer is disposed between a portion of the top surface of the active layer and the bottom surface of the contact layer. The blocking layer serves to reduce current flow between the contact layer and the portion of the active layer covered by the blocking layer. Current flow to the contact layer may occur via gridlines electrically connecting the active layer to the contact layer.
摘要翻译：太阳能电池包括有源层，阻挡层和接触层。阻挡层设置在有源层的顶表面的一部分和接触层的底表面之间。阻挡层用于减少接触层与被阻挡层覆盖的有源层的部分之间的电流。可以通过将活性层电连接到接触层的网格线来发生到接触层的电流。

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